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US 2018/0095884 A1Published application
Mass storage cache in non volatile level of multi-level system memory
AssigneeIntel Corporation
InventorsMaciej KAMINSKI, Piotr WYSOCKI, Slawomir PTAK
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Abstract
An apparatus is described. The apparatus includes a memory controller comprising logic circuitry to implement a mass storage cache in a non volatile region of a system memory. The non volatile region of the system memory is to support execution of program code directly out of the non volatile region system memory.
Claims22
An apparatus, comprising:
- a memory controller comprising logic circuitry to implement a mass storage cache in a non volatile region of a system memory, the non volatile region of the system memory to support execution of program code directly out of the non volatile region system memory.
A machine readable storage medium containing program code that when processed by a computing system causes the system to perform a method, the method comprising:
- performing a write call on a buffer within a system memory having a non volatile region and a mass storage cache within the non volatile region, the performing of the write call comprising:
- executing a cache line flush instruction to direct any cache lines of the buffer within a processor level cache to a memory controller;
- executing a fence instruction to indicate that program execution shall not continue until the cache lines have been written to system memory;
- executing a commit instruction to commit the buffer's contents to the mass storage cache.
1 more element
A computing system, comprising:
- one or more processing cores;
- a networking interface;
- a multi-level system memory;
- a memory controller comprising logic circuitry to implement a mass storage cache in a non volatile region of the multi-level system memory, the multi-level system memory to support execution of program code by way of cache line granularity accesses to the multi-level system memory.
1 more element
Dependencies are inferred from the claim text.