# US 2018/0027680 A1 · Dynamic Memory for Compute Resources in a Data Center

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- Number: US 2018/0027680 A1
- Document ID: US20180027680A1
- Status: Published application
- Kind: A1
- Application number: 15/476,915
- Filed: 2017-03-31
- Published: 2018-01-25
- Earliest claimed: 2016-07-22
- Assignees: Intel Corporation
- Inventors: MOHAN J. KUMAR; MURUGASAMY K. NACHIMUTHU
- Web page: https://patentgrep.com/patent/US20180027680A1

## CPC

- G06F 3/061: {Improving I/O performance}
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- H04L 9/14: using a plurality of keys or algorithms
- H04L 9/3247: {involving digital signatures}
- H04L 9/3263: {involving certificates, e.g. public key certificate [PKC] or attribute certificate [AC]; Public key infrastructure [PKI] arrangements (network architectures or network communication protocols for supporting authentication of entities using certificates in a packet data network H04L63/0823)}
- H04L 12/2809: {indicating that an appliance service is present in a home automation network (monitoring functionality H04L43/0817; discovery or management thereof, e.g. service location protocol [SLP] or web services, H04L67/51)}
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- H04L 41/046: comprising network management agents or mobile agents therefor
- H04L 41/0813: characterised by the conditions triggering a change of settings
- H04L 41/082: the condition being updates or upgrades of network functionality
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- H04L 41/149: for prediction of maintenance
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- H04L 67/34: {involving the movement of software or configuration parameters (network booting or remote initial program loading [RIPL] G06F9/4416)}
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- H04Q 2011/0041: {Optical control}
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- H04Q 2213/13523: bandwidth management, e.g. capacity management
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- H04W 4/80: Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
- H05K 1/0203: {Cooling of mounted components (H05K1/0272 takes precedence)}
- H05K 1/181: associated with surface mounted components
- H05K 5/0204: {Mounting supporting structures on the outside of casings}
- H05K 7/1418: {Card guides, e.g. grooves (H05K7/1425 takes precedence)}
- H05K 7/1421: {Drawers for printed circuit boards}
- H05K 7/1422: {Printed circuit boards receptacles, e.g. stacked structures, electronic circuit modules or box like frames}
- H05K 7/1447: {External wirings; Wiring ducts; Laying cables}
- H05K 7/1461: {Slidable card holders; Card stiffeners; Control or display means therefor}
- H05K 7/1485: {Servers; Data center rooms, e.g. 19-inch computer racks}
- H05K 7/1487: {Blade assemblies, e.g. blade cases or inner arrangements within a blade}
- H05K 7/1489: {characterized by the mounting of blades therein, e.g. brackets, rails, trays (H05K7/1491 takes precedence)}
- H05K 7/1491: {having cable management arrangements (management of optical cables G02B6/444; in telecommunication cabinets H04Q1/06)}
- H05K 7/1492: {having electrical distribution arrangements, e.g. power supply or data communications}
- H05K 7/1498: {Resource management, Optimisation arrangements, e.g. configuration, identification, tracking, physical location (thermal management H05K7/20836)}
- H05K 7/2039: {characterised by the heat transfer by conduction from the heat generating element to a dissipating body (arrangements for increasing/decreasing heat-transfer, e.g. fins details, F28F13/00)}
- H05K 7/20709: {for server racks or cabinets; for data centers, e.g. 19-inch computer racks}
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- H05K 7/20736: {within cabinets for removing heat from server blades}
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- G07C: TIME OR ATTENDANCE REGISTERS; REGISTERING OR INDICATING THE WORKING OF MACHINES; GENERATING RANDOM NUMBERS; VOTING OR LOTTERY APPARATUS; ARRANGEMENTS, SYSTEMS OR APPARATUS FOR CHECKING NOT PROVIDED FOR ELSEWHERE
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## Abstract

Examples may include sleds for a rack in a data center including physical compute resources and memory for the physical compute resources. The memory can be disaggregated, or organized into first level and second level memory. A first sled can comprise the physical compute resources and a first set of physical memory resources while a second sled can comprise a second set of physical memory resources. The first set of physical memory resources can be coupled to the physical compute resources via a local interface while the second set of physical memory resources can be coupled to the physical compute resources via a fabric.

## Claims

### Claim 1

A system for a data center comprising:
a rack comprising a plurality of sled spaces; and
at two or more compute sleds coupled to the rack via at two or more of the plurality of sled spaces, each of the two or more compute sleds comprising:
at least one physical compute resource;
a set of physical first level memory resources coupled to the at least one physical compute resource; and
a compute sled fabric interface; and
a memory resource sled coupled to the rack via another one of the plurality of sled spaces different than the two or more of the plurality of sled spaces, the memory resource sled comprising:
a set of physical second level memory resources; and
a second level memory sled fabric interface to couple a portion of the set of physical second level memory resources to each of the at least one physical compute resources of the two or more compute sleds via a fabric and the compute sled fabric interfaces.

### Claim 2 (depends on 1)

The system of claim 1, the sets of physical first level memory resources comprising volatile memory.

### Claim 3 (depends on 2)

The system of claim 2, the set of physical second level memory resources comprising byte-addressable write-in place nonvolatile memory.

### Claim 4 (depends on 1)

The system of claim 1, each of the at least one physical compute resources comprising a central processing unit, a field programmable gate array, a graphics processing unit, or an application specific integrated circuit.

### Claim 5 (depends on 1)

The system of claim 1, each of the two or more compute sleds comprising a first memory controller to couple the at least one physical compute resource to at least one of the set of physical first level memory resources or the portion of the set of physical second level memory resources.

### Claim 6 (depends on 5)

The system of claim 5, each of the two or more compute sleds comprising a second memory controller, the first memory controller to couple the at least one physical compute resource to the set of physical first level memory resources and the second memory controller to couple the at least one physical compute resource to the portion of the set of physical second level memory resources.

### Claim 7 (depends on 1)

The system of claim 1, the at least one physical compute resource of each of the two or more compute sleds coupled to the set of physical first level memory resources via a local interface, the local interface a peripheral component interconnect express compliant standard interface.

### Claim 8 (depends on 1)

The system of claim 1, the fabric an optical fabric.

### Claim 9 (depends on 1)

The system of claim 1, comprising a virtual infrastructure management framework to dynamically allocate the portions of the physical second level memory resources to each of the two or more compute sleds.

### Claim 10

An apparatus for a compute resource sled of a data center, comprising:
at least one physical compute resource;
a set of physical first level memory resources coupled to the at least one physical compute resource; and
a first fabric interface, the first fabric interface to couple the at least one physical compute resource to a portion of a set of physical second level memory resources via a fabric, the set of physical second level memory resources to be shared between the compute resource sled and another compute resource sled of the data center.

### Claim 11 (depends on 10)

The apparatus of claim 10, the first set of physical memory resources comprising volatile memory.

### Claim 12 (depends on 11)

The apparatus of claim 11, the second set of physical memory resources comprising three-dimensional (3D) cross-point memory.

### Claim 13 (depends on 10)

The apparatus of claim 10, the at least one physical compute resource comprising a central processing unit, a field programmable gate array, a graphics processing unit, or an application specific integrated circuit.

### Claim 14 (depends on 10)

The apparatus of claim 10, comprising a first memory controller to couple the at least one physical compute resource to at least one of the set of physical first level memory resources or portion of the set of physical second level memory resources.

### Claim 15 (depends on 14)

The apparatus of claim 14, comprising a second memory controller, the first memory controller to couple the at least one physical compute resource to the set of physical first level memory resources and the second memory controller to couple the at least one physical compute resource to the portion of the set of physical second level memory resources.

### Claim 16 (depends on 10)

The apparatus of claim 10, the at least one physical compute resource coupled to the set of physical first level memory resources via a local interface, the local interface a peripheral component interconnect express compliant standard interface.

### Claim 17 (depends on 10)

The apparatus of claim 10, the fabric an optical fabric.

### Claim 18

A method comprising:
allocating a first portion of a set of physical second level memory resources to a first compute sled;
allocating a second portion of the set of physical second level memory resources different than the first portion to a second compute sled;
coupling, via a fabric, at least one physical compute resource of the first compute sled to the first portion of the set of physical second level memory resources; and
coupling, via the fabric, at least one physical compute resource of the second compute sled to the second portion of the set of physical second level memory resources.

### Claim 19 (depends on 18)

The method of claim 18, the set of physical second level memory resources comprising three-dimensional (3D) cross-point memory.

### Claim 20 (depends on 18)

The method of claim 18, the at least one physical compute resource comprising a central processing unit, a field programmable gate array, a graphics processing unit, or an application specific integrated circuit.

### Claim 21 (depends on 18)

The method of claim 18, comprising:
composing a first virtual compute platform from the at least one physical compute resource of the first compute sled and the first portion of the set of physical second level memory resources; and
allocating the first portion of the set of physical second level memory resources to the first compute sled based on a workload to be executed by the first virtual compute platform.

### Claim 22 (depends on 21)

The method of claim 21, comprising:
composing a second virtual compute platform from the at least one physical compute resource of the second compute sled and the second portion of the set of physical second level memory resources; and
allocating the second portion of the set of physical second level memory resources to the second compute sled based on a workload to be executed by the second virtual compute platform.

### Claim 23 (depends on 22)

The method of claim 22, comprising adjusting the allocation of at least one of the first portion of the set of physical second level memory resources or the second portion of the set of physical second level memory resources.

### Claim 24 (depends on 18)

The method of claim 18, each of the first compute sled and the second compute sled comprising a set of physical first level memory resources, allocating the first portion of the set of physical second level memory resources to the first compute sled based on a quantity of the set of physical first level memory resources of the first compute sled and allocating the second portion of the set of physical second level memory resources to the second compute sled based on a quantity of the set of physical first level memory resources of the second compute sled.

### Claim 25 (depends on 24)

The method of claim 24, comprising allocating the portions of the set of physical second level memory resources to the first and the second compute sleds to achieve a ratio of the quantity to the sets of physical first level memory resources to a quantity of the portions of the set of physical second level memory resources.