# US 2018/0027652 A1 · Circuit board and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0027652 A1 - Document ID: US20180027652A1 - Status: Published application - Kind: A1 - Application number: 15/263,388 - Filed: 2016-09-13 - Published: 2018-01-25 - Earliest claimed: 2016-07-19 - Assignees: Unimicron Technology Corp. - Applicants: Unimicron Technology Corp. - Inventors: Chun-Ting Lin; Tsung-Si Wang - Web page: https://patentgrep.com/patent/US20180027652A1 ## CPC - H05K 1/0296: {Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295 (H05K1/11 takes precedence; lay-out adapted to mounted component configuration H05K1/18)} - H05K 1/09: Use of materials for the {conductive, e.g. } metallic pattern - H05K 1/113: {Via provided in pad; Pad over filled via} - H05K 3/064: {Photoresists} - H05K 3/243: {characterised by selective plating, e.g. for finish plating of pads (selective plating for making the circuit pattern H05K3/108, H05K3/182)} - H05K 3/244: {Finish plating of conductors, especially of copper conductors, e.g. for pads or lands (selective plating methods H05K3/243; finish plating of conductors made by printing techniques H05K3/246; solder as finish H05K3/3465)} - H05K 1/024: {Dielectric details, e.g. changing the dielectric material around a transmission line} - H05K 1/115: {Via connections; Lands around holes or via connections (H05K1/112 takes precedence)} - H05K 3/007: {Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier (H05K1/187, H05K3/20 and H05K3/4682 take precedence)} - H05K 3/181: {by electroless plating (adhesives therefor H05K3/387)} - H05K 3/188: {by direct electroplating} - H05K 2201/0761: Insulation resistance, e.g. of the surface of the PCB between the conductors - H05K 2201/09827: Tapered, e.g. tapered hole, via or groove - H05K 2203/0514: Photodevelopable thick film, e.g. conductive or insulating paste - H05K 2203/0571: Dual purpose resist, e.g. etch resist used as solder resist, solder resist used as plating resist - H05K 2203/058: Additional resists used for the same purpose but in different areas, i.e. not stacked - H05K 2203/0597: Resist applied over the edges or sides of conductors, e.g. for protection during etching or plating - H05K 2203/1563: Reversing the PCB - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ## Abstract A circuit board including a substrate, a patterned circuit layer and a photo-imaginable dielectric layer is provided. The substrate has a first surface and a second surface opposite to each other. The patterned circuit layer is disposed on the first surface, and a line width of the patterned circuit layer gradually reduces from the first surface towards the second surface. The photo-imaginable dielectric layer is disposed in the substrate corresponding to the patterned circuit layer. In addition, a manufacturing method of the circuit board is also proposed. ## Claims ### Claim 1 A circuit board, comprising: a substrate, having a first surface and a second surface opposite to each other; a patterned circuit layer, disposed on the first surface, and a line width of the patterned circuit layer gradually reducing from the first surface towards the second surface; and a patterned photo-imaginable dielectric layer, disposed in the substrate corresponding to the patterned circuit layer. ### Claim 2 (depends on 1) The circuit board according to claim 1, wherein a cross section outline of the patterned circuit layer is an inverted-trapezoid. ### Claim 3 (depends on 1) The circuit board according to claim 1, wherein the substrate has a plurality of through holes respectively connecting the first surface and the second surface. ### Claim 4 (depends on 1) The circuit board according to claim 1, wherein the patterned photo-imaginable dielectric layer correspondingly contacts the patterned circuit layer. ### Claim 5 (depends on 1) The circuit board according to claim 1, further comprising: a first surface finish layer, exposed on the second surface and covering a bottom surface of a part of the patterned circuit layer. ### Claim 6 (depends on 5) The circuit board according to claim 5, wherein a composite material of the first surface finish layer comprises Ni, Au or an alloy thereof. ### Claim 7 (depends on 1) The circuit board according to claim 1, further comprising: a carrier, disposed on the second surface of the substrate. ### Claim 8 (depends on 1) The circuit board according to claim 1, wherein a composite material of the substrate comprises a solder resist material. ### Claim 9 (depends on 1) The circuit board according to claim 1, further comprising: a second surface finish layer, exposed on the first surface and covering a top surface of the patterned circuit layer. ### Claim 10 (depends on 9) The circuit board according to claim 9, wherein a chip is adapted to be disposed on the first surface to electrically contact the second surface finish layer and the patterned circuit layer. ### Claim 11 A manufacturing method of a circuit board, comprising: providing a first carrier, the first carrier having a third surface and a fourth surface opposite to each other, wherein a release film and a first metal layer are respectively disposed on the third surface and the fourth surface in sequence; forming a photo-imaginable dielectric layer on the first metal layer, and patterning the photo-imaginable dielectric layer; forming a patterned dry film layer on the photo-imaginable dielectric layer, and the patterned dry film layer exposing a part of the first metal layer and the photo-imaginable dielectric layer; electroplating a second metal layer on the part of the first metal layer by using the patterned dry film layer as an electroplating mask, and forming a first surface finish layer on the second metal layer; removing the patterned dry film layer to expose another part of the photo-imaginable dielectric layer and the first metal layer; etching the first metal layer by using the photo-imaginable dielectric layer as an etching mask to form a patterned circuit layer on the release film; coating a solder resist material on the patterned circuit layer and the photo-imaginable dielectric layer to form a substrate, and exposing the first surface finish layer, wherein the substrate has a first surface and a second surface opposite to each other, the first surface contacts the release film, and a line width of the patterned circuit layer gradually reduces from the first surface towards the second surface; disposing a second carrier on the second surface, and removing the first carrier from the first surface through the release film; and forming a second surface finish layer on the patterned circuit layer exposed on the first surface. ### Claim 12 (depends on 11) The manufacturing method of the circuit board according to claim 11, wherein a method of forming the second surface finish layer comprises performing an electroless plating manufacturing process.