# US 2018/0027648 A1 · Interconnect structure and method of manufacturing the same

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- Number: US 2018/0027648 A1
- Document ID: US20180027648A1
- Status: Published application
- Kind: A1
- Application number: 15/723,099
- Filed: 2017-10-02
- Published: 2018-01-25
- Earliest claimed: 2016-02-04
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Jiun-Yi WU; Chien-Hsun LEE; Chewn-Pu JOU; Fu-Lung HSUEH
- Web page: https://patentgrep.com/patent/US20180027648A1

## CPC

- H05K 1/0216: {Reduction of cross-talk, noise or electromagnetic interference (grounding H05K1/0215)}
- H05K 1/0222: {for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence}
- H05K 1/024: {Dielectric details, e.g. changing the dielectric material around a transmission line}
- H05K 1/113: {Via provided in pad; Pad over filled via}
- H05K 1/115: {Via connections; Lands around holes or via connections (H05K1/112 takes precedence)}
- H05K 3/0047: {Drilling of holes}
- H05K 3/4007: {Surface contacts, e.g. bumps (H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3465)}
- H05K 3/423: {characterised by electroplating method}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 70/092: {Adapting interconnections, e.g. making engineering changes, repairing}
- H10W 70/095: {of vias therein}
- H10W 70/635: {Through-vias}
- H05K 1/0245: {Lay-out of balanced signal pairs, e.g. differential lines or twisted lines}
- H05K 3/4038: {Through-connections; Vertical interconnect access [VIA] connections (H05K3/403, H05K3/42 take precedence)}
- H05K 3/42: Plated through-holes {or plated via connections}
- H05K 2201/0723: provided by an inner layer of PCB
- H05K 2201/09545: Plated through-holes or blind vias without lands
- H05K 2201/0959: Plated through-holes or plated blind vias filled with insulating material
- H05K 2201/09645: Patterning on via walls; Plural lands around one hole
- Y10T 29/49165: by forming conductive walled aperture in base
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

A method for manufacturing an interconnect structure is provided. The method includes the following steps. An opening is through a substrate. A low-k dielectric block is formed in the opening. At least one first via is formed through the low-k dielectric block. A first conductor is formed in the first via.

## Claims

### Claim 1

A method comprising:
forming an opening through a substrate;
forming a low-k dielectric block in the opening;
forming at least one first via through the low-k dielectric block; and
forming a first conductor in the first via.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first conductor is formed on a sidewall of the first via.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first conductor is formed by electroplating.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
forming a plug in the first via after the forming the first conductor, such that the plug is surrounded by the first conductor.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
forming a shielding element on a sidewall of the opening before the forming the low-k dielectric block.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
forming a pad over the first conductor;
forming a dielectric layer over the substrate, the low-k dielectric block, and the pad;
forming at least one second via in the dielectric layer to expose the pad; and
forming a second conductor in the second via, such that the second conductor is over and in contact with the pad.

### Claim 7 (depends on 1)

The method of claim 1, wherein the opening is formed by mechanical drilling, mechanical routing, laser drilling, photolithography, or combinations thereof.

### Claim 8 (depends on 1)

The method of claim 1, wherein the first via is formed by mechanical drilling, mechanical routing, laser drilling, photolithography, or combinations thereof.

### Claim 9 (depends on 1)

The method of claim 1, wherein the forming the low-k dielectric block comprises:
plugging the low-k dielectric block into the opening.

### Claim 10 (depends on 1)

The method of claim 1, further comprising:
removing an excess portion of the low-k dielectric block out of the opening.

### Claim 11 (depends on 10)

The method of claim 10, wherein the removing comprises:
grinding the excess portion of the low-k dielectric block.

### Claim 12 (depends on 1)

The method of claim 1, wherein the forming the first conductor is performed such that the first conductor has a portion protruding out of the first via and a top surface of the protruding portion is in contact with a bottom surface of the low-k dielectric block.

### Claim 13

A method comprising:
forming an opening in a substrate;
forming a dielectric block in the opening;
forming at least one first via in the dielectric block;
forming a first conductor in the first via;
forming a dielectric layer over the substrate and the first conductor;
forming at least one second via in the dielectric layer; and
forming a second conductor in the second via, such that the second conductor is electrically connected to the first conductor.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
forming a pad over the first conductor before the forming the dielectric layer.

### Claim 15 (depends on 13)

The method of claim 13, wherein the dielectric block has a lower dielectric constant than the substrate.

### Claim 16 (depends on 13)

The method of claim 13, further comprising:
forming a shielding element on a sidewall of the opening and on a top surface of the substrate.

### Claim 17

A method comprising:
forming an opening in a substrate;
forming a shielding element on a sidewall of the opening;
forming a dielectric block in the opening, such that the dielectric block is surrounded by the shielding element, wherein the dielectric block has a lower dielectric constant than the substrate;
forming at least one first via in the dielectric block; and
forming a first conductor in the first via.

### Claim 18 (depends on 17)

The method of claim 17, wherein the forming the dielectric block comprises:
plugging the dielectric block into the opening.

### Claim 19 (depends on 17)

The method of claim 17, further comprising:
forming a dielectric layer over the substrate and the first conductor;
forming at least one second via in the dielectric layer; and
filling the second via with a second conductor, such that the second conductor is electrically connected to the first conductor.

### Claim 20 (depends on 19)

The method of claim 19, further comprising:
forming a pad over the first conductor before the forming the dielectric layer.