# US 2018/0026779 A1 · Apparatus and method for centering clock signal in cumulative data eye of parallel data in clock forwarded links

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- Number: US 2018/0026779 A1
- Document ID: US20180026779A1
- Status: Published application
- Kind: A1
- Application number: 15/214,296
- Filed: 2016-07-19
- Published: 2018-01-25
- Earliest claimed: 2016-07-19
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Robert Michael Bunce
- Web page: https://patentgrep.com/patent/US20180026779A1

## CPC

- H04L 7/0037: {Delay of clock signal}
- H03K 5/135: by the use of time reference signals, e.g. clock signals
- H03L 7/0807: {concerning mainly a recovery circuit for the reference signal}
- H04L 1/0042: {Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape (H04L1/0067 takes precedence)}
- H04L 7/0008: {Synchronisation information channels, e.g. clock distribution lines}
- H04L 7/0012: {by comparing receiver clock with transmitter clock}
- H04L 7/0337: {Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals}
- H04L 25/14: Channel dividing arrangements {, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

An apparatus for setting the timing of a triggering edge of a clock signal with respect to received parallel data. The apparatus includes a set of flip-flops including respective data inputs, respective clock inputs, and respective data outputs, wherein the set of flip-flops are configured to generate a set of output data at the data output based on parallel data applied to the respective data inputs in response to a triggering edge of a clock signal applied to the clock inputs; a variable delay element configured to apply a calibrated delay to the clock signal; and a controller configured to generate a control signal for the variable delay element to apply the calibrated delay to the clock signal based on the set of output data generated at the data outputs of the set of flip-flops.

## Claims

### Claim 1

An apparatus, comprising:
a set of flip-flops including data inputs, clock inputs, and data outputs, respectively, wherein the set of flip-flops are configured to generate a set of output data at the data outputs based on a set of input data applied to the data inputs in response to a triggering edge of a delayed clock signal commonly applied to the clock inputs, respectively;
a variable delay element configured to apply a calibrated delay to a clock signal to generate the calibrated clock signal; and
a controller configured to generate a control signal for the variable delay element to apply the calibrated delay to the clock signal based on the set of output data generated at the data outputs of the flip-flops, respectively.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the controller is configured to generate the control signal such that the triggering edge of the delayed clock signal at the clock inputs substantially coincides with a collective valid data region of the set of input data at the data inputs of the flip-flops.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the controller is configured to generate the control signal such that the triggering edge of the delayed clock signal at the clock inputs coincides substantially with a center of a collective valid data region of the set of input data at the data inputs of the flip-flops.

### Claim 4 (depends on 1)

An apparatus of claim 1, comprising:
a set of flip-flops including data inputs, clock inputs, and data outputs, respectively, wherein the set of flip-flops are configured to generate a set of output data at the data outputs based on a set of input data applied to the data inputs in response to a triggering edge of a clock signal applied to the clock inputs, respectively;
a variable delay element configured to apply a calibrated delay to the clock signal; and
a controller configured to generate a control signal for the variable delay element to apply the calibrated delay to the clock signal based on the set of output data generated at the data outputs of the flip-flops, respectively, wherein the controller is configured to generate the control signal by at least:
controlling the variable delay element to apply a set of monotonically changing delays to the clock signal;
receiving the set of output data from the data outputs of the set of flip-flops for each delay of the set of monotonically changing delays;
assigning a first value in response to each set of output data being all logic zeros;
assigning a second value in response to each set of output data being all logic ones;
assigning a third value in response to each set of output data being a mix of logic ones and logic zeros;
generating an array comprising a set of values based on the first, second, and third values; and
generating the control signal based on the array.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein the set of values of the array correspond with the set of monotonically changing delays of the variable delay element, respectively.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein the controller is configured to generate the control signal such that the calibrated delay corresponds to one of the set of monotonically changing delays that corresponds to one of a consecutive string of first values or second values of the array.

### Claim 7 (depends on 5)

The apparatus of claim 5, wherein the controller is configured to generate the control signal such that the calibrated delay corresponds to one of the set of monotonically changing delays that corresponds to substantially a center of a consecutive string of first values or second values of the array.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein the consecutive string of first values or second values is the longest consecutive strings of the same values of the array.

### Claim 9

A method, comprising:
receiving a set of input data at respective data inputs of a set of flip-flops;
receiving a clock signal commonly at respective clock inputs of the set of flip-flops;
generating a set of output data at respective data outputs of the set of flip-flops in response to a triggering edge of the clock signal; and
setting a timing of the triggering edge of the clock signal with respect to the input data based on the output data.

### Claim 10 (depends on 9)

The method of claim 9, wherein setting the timing of the triggering edge of the clock signal comprises setting the triggering edge of the clock signal to substantially coincide with a collective valid data region of the set of input data at the data inputs of the flip-flops.

### Claim 11 (depends on 9)

The method of claim 9, wherein setting the timing of the triggering edge of the clock signal comprises setting the timing of the triggering edge of the clock signal to coincide substantially with a center of a collective valid data region of the set of input data at the data inputs of the flip-flops.

### Claim 12 (depends on 9)

A method of claim 9, comprising:
receiving a set of input data at respective data inputs of a set of flip-flops;
receiving a clock signal at respective clock inputs of the set of flip-flops;
generating a set of output data at respective data outputs of the set of flip-flops in response to a triggering edge of the clock signal; and
setting a timing of the triggering edge of the clock signal with respect to the input data based on the output data, wherein setting the timing of the triggering edge of the clock signal comprises:
applying a set of monotonically changing delays to the timing of the triggering edge of the clock signal with respect to the input data at the respective data inputs of the flip-flops;
receiving the set of output data from the data outputs of the set of flip-flops for each delay of the timing of the triggering edge;
assigning a first value in response to each set of output data being all logic zeros;
assigning a second value in response to each set of output data being all logic ones;
assigning a third value in response to each set of output data being a mix of logic ones and logic zeros;
generating an array comprising a set of values based on the first, second, and third values; and
generating the control signal based on the array.

### Claim 13 (depends on 12)

The method of claim 12, wherein the set of values of the array correspond with the set of monotonically changing delays of the variable delay element, respectively.

### Claim 14 (depends on 13)

The method of claim 13, wherein setting the timing of the triggering edge of the clock signal comprises selecting one of the set of monotonically changing delays that corresponds to one of a consecutive string of first values or second values of the array.

### Claim 15 (depends on 13)

The method of claim 13, wherein setting the timing of the triggering edge of the clock signal comprises selecting one of the set of monotonically changing delays that corresponds to substantially a center of a consecutive string of first values or second values of the array.

### Claim 16 (depends on 15)

The method of claim 15, wherein the consecutive string of first values or second values is the longest consecutive strings of the same values of the array.

### Claim 17

An apparatus, comprising:
means for receiving a set of input data at respective data inputs of a set of flip-flops;
means for receiving a clock signal commonly at respective clock inputs of the set of flip-flops;
means for generating a set of output data at respective data outputs of the set of flip-flops in response to a triggering edge of the clock signal; and
means for setting a timing of the triggering edge of the clock signal with respect to the input data based on the output data.

### Claim 18 (depends on 17)

The apparatus of claim 17, wherein the means for setting the timing of the triggering edge of the clock signal comprises means for setting the triggering edge of the clock signal to substantially coincide with a collective valid data region of the set of input data at the data inputs of the flip-flops.

### Claim 19 (depends on 17)

The apparatus of claim 17, wherein the means for setting the timing of the triggering edge of the clock signal comprises means for setting the timing of the triggering edge of the clock signal to coincide substantially with at a center of a collective valid data region of the set of input data at the data inputs of the flip-flops.

### Claim 20

An apparatus, comprising:
means for receiving a set of input data at respective data inputs of a set of flip-flops;
means for receiving a clock signal at respective clock inputs of the set of flip-flops;
means for generating a set of output data at respective data outputs of the set of flip-flops in response to a triggering edge of the clock signal; and
means for setting a timing of the triggering edge of the clock signal with respect to the input data based on the output data, wherein the means for setting the timing of the triggering edge of the clock signal comprises:
means for applying a set of monotonically changing delays to the timing of the triggering edge of the clock signal with respect to the input data at the respective data inputs of the flip-flops;
means for receiving the set of output data from the data outputs of the set of flip-flops for each delay of the timing of the triggering edge;
means for assigning a first value in response to each set of output data being all logic zeros;
means for assigning a second value in response to each set of output data being all logic ones;
means for assigning a third value in response to each set of output data being a mix of logic ones and logic zeros;
means for generating an array comprising a set of values based on the first, second, and third values; and
means for generating the control signal based on the array.

### Claim 21 (depends on 20)

The apparatus of claim 20, wherein the set of values of the array corresponds with the set of monotonically changing delays of the variable delay element, respectively.

### Claim 22 (depends on 21)

The apparatus of claim 21, wherein the means for setting the timing of the triggering edge of the clock signal comprises means for selecting one of the set of monotonically changing delays that corresponds to one of a consecutive string of first values or second values of the array.

### Claim 23 (depends on 21)

The apparatus of claim 21, wherein the means for setting the timing of the triggering edge of the clock signal comprises means for selecting one of the set of monotonically changing delays that corresponds to substantially a center of a consecutive string of first values or second values of the array.

### Claim 24 (depends on 23)

The apparatus of claim 23, wherein the consecutive string of first values or second values is the longest consecutive strings of the same values of the array.

### Claim 25

An apparatus, comprising:
a flip-flop including a data input, a clock input, and a data output, wherein the flip-flop is configured to generate an output data at the data output based on an input data applied to the data input in response to a triggering edge of a clock signal applied to the clock input;
a variable delay element configured to apply a calibrated delay to the input data signal; and
a controller configured to generate a control signal for the variable delay element to apply the calibrated delay to the input data based on the output data generated at the data output of the flip-flop.

### Claim 26 (depends on 25)

The apparatus of claim 25, wherein the controller is configured to generate the control signal such that the triggering edge of the clock signal at the clock input substantially coincides with a valid data region of the input data at the data input of the flip-flop.

### Claim 27 (depends on 25)

The apparatus of claim 25, wherein the controller is configured to generate the control signal by at least:
controlling the variable delay element to apply a set of monotonically changing delays to the data signal;
receiving the output data from the data output of the flip-flop for each delay of the set of monotonically changing delays;
generating a word comprising a set of the output data corresponding to the set of the monotonically changing delays of the data signal, respectively; and
generating the control signal based on the word.

### Claim 28 (depends on 27)

The apparatus of claim 27, wherein the controller is configured to generate the control signal such that the calibrated delay corresponds to one of the set of monotonically changing delays that corresponds to one of a consecutive string of logic ones or logic zeros of the word.

### Claim 29 (depends on 27)

The apparatus of claim 27, wherein the controller is configured to generate the control signal such that the calibrated delay corresponds to one of the set of monotonically changing delays that corresponds to substantially a center of a consecutive string of logic ones or logic zeros of the word.

### Claim 30 (depends on 25)

The apparatus of claim 25, further comprising:
a transmitting device configured to generate and transmit the input data, wherein the transmitting device comprises the variable delay element; and
a receiving device configured to receive the input data from the transmitting device, wherein the receiving device comprises the flip-flop and the controller.