# US 2018/0026748 A1 · Header processing device, processor, and electronic device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2018/0026748 A1
- Document ID: US20180026748A1
- Status: Published application
- Kind: A1
- Application number: 15/428,347
- Filed: 2017-02-09
- Published: 2018-01-25
- Earliest claimed: 2016-07-20
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Woon Yong JO; Dae Keon PARK; June Hee LEE
- Web page: https://patentgrep.com/patent/US20180026748A1

## CPC

- H04L 1/0061: {Error detection codes}
- H03M 13/096: {Checksums}
- H04L 67/12: specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
- H04L 69/22: Parsing or analysis of headers
- H03M 13/09: Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A header processing device includes an error detector, a controller, and a reallocator. The error detector detects an error in a header in a packet and outputs a header error detection result. The controller selects first and second information from the header based on information corresponding to a type of the header and the header error detection result. The reallocator merges the first and second information and generates a header with a common format different from a format of the header.

## Claims

### Claim 1

A header processing device, comprising:
an error detector to detect an error in a header in a packet and output a header error detection result;
a controller to select first information and second information from the header based on information corresponding to a type of the header and the header error detection result; and
a reallocator to merge the first and second information and generate a header with a common format different from a format of the header.

### Claim 2 (depends on 1)

The device as claimed in claim 1, wherein the error detector is to detect an error in the header using an error correction code (ECC) in the header.

### Claim 3 (depends on 2)

The device as claimed in claim 2, wherein:
when an error in the header is detected, the error detector is to generate and transmit an error interrupt to a core processor of an electronic device including the header processing device.

### Claim 4 (depends on 3)

The device as claimed in claim 3, wherein:
when the error interrupt is generated, the reallocator is not to generate the header with the common format.

### Claim 5 (depends on 1)

The device as claimed in claim 1, wherein the error detector is to detect an error in each of a plurality of unit headers in the header based on a cyclic redundancy check (CRC) checksum.

### Claim 6 (depends on 5)

The device as claimed in claim 5, wherein:
when an error in all of the unit headers in the header is detected, the error detector is to generate the error interrupt in a core processor of an electronic device including the header processing device.

### Claim 7 (depends on 6)

The device as claimed in claim 6, wherein:
when the error interrupt is generated, the reallocator is not to generate the header with a common format.

### Claim 8 (depends on 1)

The device as claimed in claim 1, wherein the controller includes:
a finite state machine FSM to transmit at least one portion of the header and data in the packet to the error detector and the reallocator based on the information corresponding to the type of the header; and
a header selector to generate a signal to select the first information and the second information and to provide the signal to the reallocator.

### Claim 9 (depends on 8)

The device as claimed in claim 8, wherein:
when an error in the header is not detected using ECC in the header, the header selector is to generate the signal to select the first information and the second information in the header.

### Claim 10 (depends on 8)

The device as claimed in claim 8, wherein the header selector is to generate the signal to select the first information and the second information in a header in which an error is not detected, among the headers in the header.

### Claim 11 (depends on 1)

The device as claimed in claim 1, wherein the reallocator includes:
a first input to receive at least one piece of first information in the header and to output first information selected by the controller;
a second input to receive at least one piece of second information in the header and to output second information selected by the controller;
a header merger to merge the first and second information output by the first input and the second input, respectively, and to generate and output the header having the common format;
a payload merger to receive data in the packet and merge and output the data; and
an output to merge and output the header having the common format and the data respectively output by the header merger and the payload merger.

### Claim 12 (depends on 1)

The device as claimed in claim 1, wherein the header is to be provided as a D-PHY header and a C-PHY header.

### Claim 13 (depends on 12)

The device as claimed in claim 12, wherein the first information is to be provided as a data ID in the header, and the second information is to be provided as packet data field information in the header.

### Claim 14

(canceled)

### Claim 15

A processor, comprising:
a first physical layer to receive a first packet with a first header;
a second physical layer to receiving a second packet with a second header;
a link layer to convert the first header and the second header in the first packet and the second packet, respectively, to a third header, the link layer to output data through parsing and data interleaving of the third header; and
a core processor to process the data output by the link layer.

### Claim 16 (depends on 15)

The processor as claimed in claim 15, wherein the link layer includes:
a header processor to convert the first header and the second header to the third header, the header processor including an error detector to detect an error in the first header and the second header and output a header error detector;
a controller to select first information and second information from the first header and the second header based on information corresponding to a type of header in the first packet and the second packet and a header error detection result; and
a reallocator to merge the first and second information and to generate the third header.

### Claim at position 17

17-22. (canceled)

### Claim 23 (depends on 16)

The processor as claimed in claim 16, wherein the controller includes”
a Finite State Machine FSM to transmit at least one portion of a header and data in each of the first packet and the second packet to the error detector and the reallocator based on information corresponding to a type of header; and
a header selector to generate a signal to select the first and second information and to provide the signal to the reallocator.

### Claim 24 (depends on 23)

The processor as claimed in claim 23, wherein:
when an error in the first header is not detected using ECC in the first header, the header selector is to generate the signal to select the first and second information in the first header.

### Claim 25 (depends on 24)

The processor as claimed in claim 24, wherein the header selector is to generate the signal to select the first and second information in a unit header in which an error is not detected, among the unit headers in the second header.

### Claim 26 (depends on 16)

The processor as claimed in claim 16, wherein the reallocator includes:
a first input to receive at least one piece of first information in the first header and the second header and output first information selected by the controller
a second input to receive at least one piece of second information in the first and second headers and output second information selected by the controller;
a header merger to merge the first and second information output by the first and second inputs, respectively, and to generate and output the third header;
a payload merger to receive data in the first packet and the second packet and to merge and output the data; and
an output to merge and output the third header and the data output by the header merger and the payload merger, respectively.

### Claim at position 22

27-30. (canceled)

### Claim 31

An apparatus, comprising:
first logic to receive a first packet with a first header format;
second logic to receive a second packet with a second header format;
third logic to generate a third header format based on the first header format and the second header format; and
fourth logic to output third and fourth packets including the third header format with data in the first and second packets respectively, wherein the first header format is different from the second header format and wherein the third header format is different from the first and second header formats.

### Claim at position 24

32-35. (canceled)