# US 2018/0026658 A1 · Ldpc decoder, semiconductor memory system and operating method thereof

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- Number: US 2018/0026658 A1
- Document ID: US20180026658A1
- Status: Published application
- Kind: A1
- Application number: 15/599,550
- Filed: 2017-05-19
- Published: 2018-01-25
- Earliest claimed: 2016-07-21
- Assignees: SK hynix Inc.; Korea Advanced Institute of Science and Technology
- Applicants: SK hynix Inc.; Korea Advanced Institute of Science and Technology
- Inventors: In-Cheol PARK; Jaehwan JUNG
- Web page: https://patentgrep.com/patent/US20180026658A1

## CPC

- H03M 13/1105: {Decoding}
- G06F 11/10: Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F 11/1012: {using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence)}
- H03M 13/1108: {Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping}
- H03M 13/1111: {Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms}
- H03M 13/116: {Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices}
- H03M 13/1171: {Parity-check or generator matrices with non-binary elements, e.g. for non-binary LDPC codes}
- H03M 13/2957: {Turbo codes and decoding}
- H03M 13/3707: {Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code}
- H03M 13/6325: {Error control coding in combination with demodulation}
- H03M 13/6343: {Error control coding in combination with techniques for partial response channels, e.g. recording}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

An operation method of a LPC decoder includes: initializing variable nodes of a Tanner graph representing a parity check matrix; performing a check node update to check nodes of the Tanner graph based on variable node values of the variable nodes; performing a variable node update when there are USC nodes among the updated check nodes as a result of the check node update; and repeating the performing of the check node update and the variable node update when there are USC nodes as the result of the check node update, wherein the performing of the variable node update includes: selecting among the variable nodes a predetermined number of variable nodes having a USC value greater than a threshold; and flipping the variable node values of the selected variable nodes, and wherein the USC value is a number of the USC nodes linked to one of the variable nodes.

## Claims

### Claim 1

An operation method of a Low Density Parity Check (LDPC) decoder, the operation method comprising:
initializing variable nodes of a Tanner graph representing a parity check matrix defining an LDPC code;
performing a check node update to check nodes of the Tanner graph based on variable node values of the variable nodes;
performing a variable node update when there are one or more unsatisfied syndrome check (USC) nodes among the updated check nodes as a result of the check node update; and
repeating the performing of the check node update and the variable node update when there are one or more USC nodes as the result of the check node update,
wherein the performing of the variable node update includes:
selecting among the variable nodes a predetermined number of variable nodes having a USC value greater than a predetermined threshold; and
flipping the variable node values of the selected variable nodes, and
wherein the USC value is a number of the USC nodes linked to corresponding one of the variable nodes.

### Claim 2 (depends on 1)

The operation method of claim 1, wherein the variable nodes are selected according to an order of the USC values.

### Claim 3 (depends on 1)

The operation method of claim 1, wherein the selecting the predetermined number of variable nodes includes:
dividing the variable nodes into a predetermined number of groups; and
selecting variable nodes having greatest USC values in the respective groups.

### Claim 4 (depends on 1)

The operation method of claim 1, wherein the predetermined threshold is variable according to a repetition number of the variable node update.

### Claim 5 (depends on 1)

The operation method of claim 1 wherein the predetermined maximum number is variable according to a repetition number of the variable node update.

### Claim 6 (depends on 1)

The operation method of claim 1, further comprising determining a decoding of the LDPC decoder as successful when there is no USC nodes as the result of the, check node update.

### Claim 7

A Low Density Parity Check (LDPC) decoder comprising:
a first unit suitable for initializing variable nodes of a Tanner graph representing a parity check matrix defining an LDPC code;
a second unit suitable for performing a check node update to check nodes of the Tanner graph based on variable node values of the variable nodes; and
a third unit suitable for performing a variable node update when there is one or more unsatisfied syndrome check (USC) nodes among the updated check nodes as a result of the check node update, wherein the second and third units repeat the check node update and the variable node update when there is one or more USC nodes as the result of the check node update,
wherein the third unit includes;
a first part suitable for selecting, among the variable nodes, a predetermined number of variable nodes having an USC value greater than a predetermined threshold; and
a second part suitable for flipping the variable node values of the selected variable nodes, and
wherein the USC value is a number of the USC nodes linked to corresponding one of the variable nodes.

### Claim 8 (depends on 7)

The LDPC decoder of claim 7, wherein the first part selects the variable nodes in order of the USC values among the variable nodes having the USC value.

### Claim 9 (depends on 7)

The LDPC decoder of claim 7, wherein the first part selects the variable nodes by dividing the variable nodes into the predetermined number of groups, and selecting variable nodes having greatest USC values in the respective groups,

### Claim 10 (depends on 7)

The LDPC decoder of claim 7, wherein the predetermined threshold is variable according to a repetition number of the variable node update.

### Claim 11 (depends on 7)

The LDPC decoder of claim 7, wherein the predetermined maximum number is variable according to a repetition number of the variable node update.

### Claim 12 (depends on 7)

The LDPC decoder of claim 7, further comprising a fourth unit suitable for determining a decoding of the LDPC decoder as successful when there is no USC nodes as the result of the check node update.

### Claim 13

A semiconductor memory system comprising:
a set conductor memory device; and
a Low Density Parity Check (LDPC) decoder,
wherein the LDPC decoder includes:
a first unit suitable for initializing variable nodes of a Tanner graph representing a parity check matrix defining an LDPC code;
a second unit suitable for performing a check node update to check nodes of the Tanner graph based on variable node values of the variable nodes; and
a third unit suitable for performing a variable node update when there is one or more unsatisfied syndrome check (USC) nodes among the updated check nodes as a result of the check node update,
wherein the second and third units repeat the check node update and the variable node update when there is one or more USC nodes as the result of the check node update,
wherein the third unit includes:
a first part suitable for selecting, among the variable nodes, a predetermined number of variable nodes having an USC value greater than a predetermined threshold; and
a second part suitable for flipping the variable node values of the selected variable nodes, and
wherein the USC value is a number of the USC nodes inked to corresponding one of the variable nodes.

### Claim 14 (depends on 13)

The semiconductor memory system of claim 13, wherein the first part selects the variable nodes according to an order of the USC values among the variable nodes having the USC value.

### Claim 15 (depends on 13)

The semiconductor memory system of claim 13, wherein the first part selects the variable nodes by dividing the variable nodes into a predetermined number of groups, and selecting variable nodes having greatest USC values in the respective groups.

### Claim 16 (depends on 13)

The semiconductor memory system of claim 13 wherein the predetermined threshold is variable according to a repetition number of the variable node update.

### Claim 17 (depends on 13)

The semiconductor memory system of claim 13, wherein the predetermined maximum flip number is variable according to a repetition number of the variable node update.

### Claim 18 (depends on 13)

The semiconductor memory system of claim 13, wherein the LDPC decoder further includes a fourth unit suitable for determining a decoding of the LDPC decoder as successful when there is no USC nodes as the result of the check node update.