# US 2018/0026657 A1 · High-speed serial data receiving apparatus

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- Number: US 2018/0026657 A1
- Document ID: US20180026657A1
- Status: Published application
- Kind: A1
- Application number: 15/550,059
- Filed: 2015-02-12
- Published: 2018-01-25
- Earliest claimed: 2015-02-10
- Assignees: Hanwha Techwin Co., Ltd.
- Applicants: Hanwha Techwin Co., Ltd.
- Inventors: Young Su LEE
- Web page: https://patentgrep.com/patent/US20180026657A1

## CPC

- H03M 9/00: Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00)
- H03K 5/135: by the use of time reference signals, e.g. clock signals
- H04L 7/04: Speed or phase control by synchronisation signals {(H04L7/0075 takes precedence)}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

Provided is a high-speed serial data receiving apparatus including: a clock converter configured to convert a serial clock into a parallel clock; a data converter configured to convert a serial data packet into N parallel data packets and outputting the N parallel data packets; a synchronization signal detector configured to receive the N parallel data packets and the parallel clock, and detecting a data start synchronization of the N parallel data packets output from the data converter by comparing the parallel data packets with a synchronization code of N bits set in advance; and an error compensation unit configured to detect and compensate for a skew between parallel clock and data.

## Claims

### Claim 1

A high-speed serial data receiving apparatus comprising:
a clock converter configured to convert a serial clock into a parallel clock;
a data converter configured to convert a serial data packet into N parallel data packets and output the N parallel data packets;
a synchronization signal detector configured to receive the N parallel data packets and the parallel clock, and detect data start synchronization of the N parallel data packets output from the data converter by comparing the parallel data packets with a synchronization code of preset N bits; and
an error compensation unit configured to detect a clock skew between parallel clocks and compensate for the clock skew.

### Claim 2 (depends on 1)

The high-speed serial data receiving apparatus of claim 1, wherein the data converter converts the serial data packet into N parallel data packets by sampling the serial data packet into N flip-flops based on the serial clock.

### Claim 3 (depends on 2)

The high-speed serial data receiving apparatus of claim 2, wherein the data converter outputs the N parallel data packets by synchronizing the N parallel data packets by using the parallel clock.

### Claim 4 (depends on 1)

The high-speed serial data receiving apparatus of claim 1, wherein the clock converter comprises:
a counter configured to receive a selection signal value that is selected between a single data rate (SDR) and a double data rate (DDR), and the serial clock, as input values; and
a flip-flop configured to receive an output value of the counter and the serial clock, as input values, and output the parallel clock.

### Claim 5 (depends on 1)

The high-speed serial data receiving apparatus of claim 1, wherein the clock converter outputs a parallel clock that is slower by 1/N than the serial clock, when the data converter is a deserializer of an SDR type.

### Claim 6 (depends on 1)

The high-speed serial data receiving apparatus of claim 1, wherein the clock converter outputs a parallel clock that is slower by 2/N than the serial clock, when the data converter is a deserializer of a DDR type.

### Claim 7 (depends on 1)

The high-speed serial data receiving apparatus of claim 1, wherein, when the data converter is a deserializer of the SDR type, the serial data packet is sampled as N flip-flops at every rising edge of the serial clock to generate a parallel data packet of N bits, and is sampled at every falling edge of the parallel clock input in order to output a parallel data packet that is synchronized with the parallel clock.

### Claim 8 (depends on 1)

The high-speed serial data receiving apparatus of claim 1, wherein, when the data converter is a deserializer of the DDR type, the serial data packet is sampled as N flip-flops at a rising edge and a falling edge of the serial clock to generate a parallel data packet of N bits, and is sampled at a rising edge of the parallel clock input in order to output a parallel data packet that is synchronized with the parallel clock.

### Claim 9 (depends on 1)

The high-speed serial data receiving apparatus of claim 1, wherein the synchronization signal detector shifts the parallel data packet by one bit sequentially to a maximum N-th bit by using an N bit shifted out register, determines whether each parallel data packet shifted from a first bit to the N-th bit matches a synchronization code that is set in advance, and detects a data start synchronization signal based on a parallel data packet that matches the synchronization code.

### Claim 10 (depends on 9)

The high-speed serial data receiving apparatus of claim 9, wherein the error compensation unit detects an amount of shifted bits of the parallel data packet matching the synchronization code as a clock skew based on the parallel data packet corresponding to the synchronization code, and compensates for the clock skew.

### Claim 11 (depends on 9)

The high-speed serial data receiving apparatus of claim 9, wherein the error compensation unit detects and outputs the parallel data packet matching the synchronization code that is set in advance by using a multiplexer.

### Claim 12

A method of converting data into parallel data in a high-speed serial data receiving apparatus, the method comprising:
converting a serial clock into a parallel clock in a clock converter;
converting a serial data packet into N parallel data packets and outputting the N parallel data packets by a data converter;
detecting a synchronization of the N parallel data packets output from the data converter by the synchronization signal detector; and
detecting and compensating for a clock skew between parallel clocks by an error compensation unit.

### Claim 13 (depends on 12)

The method of claim 12, wherein the clock converter outputs a parallel clock that is slower by 1/N than the serial clock, when the data converter is a deserializer of an SDR type.

### Claim 14 (depends on 12)

The method of claim 12, wherein the clock converter outputs a parallel clock that is slower by 2/N than the serial clock, when the data converter is a deserializer of a DDR type.

### Claim 15 (depends on 12)

The method of claim 12, wherein, when the data converter is a deserializer of the SDR type, the serial data packet is sampled as N flip-flops at every rising edge of the serial clock to generate a parallel data packet of N bits, and is sampled at every falling edge of the parallel clock input in order to output a parallel data packet that is synchronized with the parallel clock.

### Claim 16 (depends on 12)

The method of claim 12, wherein, when the data converter is a deserializer of the DDR type, the serial data packet is sampled as N flip-flops at a rising edge and a falling edge of the serial clock to generate a parallel data packet of N bits, and is sampled at a rising edge of the parallel clock input in order to output a parallel data packet that is synchronized with the parallel clock.