# US 2018/0026645 A1 · Magnetoelectric Computational Devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0026645 A1 - Document ID: US20180026645A1 - Status: Published application - Kind: A1 - Application number: 15/654,278 - Filed: 2017-07-19 - Published: 2018-01-25 - Earliest claimed: 2016-07-19 - Assignees: Georgia Tech Research Corporation - Applicants: Georgia Tech Research Corporation - Inventors: Chenyun Pan; Sourav Dutta; Azad Naeemi - Web page: https://patentgrep.com/patent/US20180026645A1 ## CPC - H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) - H01F 10/14: containing iron or nickel ({H01F10/126} , H01F10/13, H01F10/16 take precedence) - H01F 10/16: containing cobalt ({H01F10/126} , H01F10/13 take precedence) - H01F 10/3218: {Exchange coupling of magnetic films via an antiferromagnetic interface (H01F10/3268 takes precedence)} - H01F 10/3268: {the exchange coupling being asymmetric, e.g. by use of additional pinning, by using antiferromagnetic or ferromagnetic coupling interface, i.e. so-called spin-valve [SV] structure, e.g. NiFe/Cu/NiFe/FeMn} - H10B 61/00: Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices - H10N 50/10: Magnetoresistive devices - H10N 50/80: Constructional details - H10N 50/85: Materials of the active region - H10N 59/00: Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00 (MRAM devices H10B61/00) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H01F: MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES - H10B: ELECTRONIC MEMORY DEVICES - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR ## Abstract Embodiments of the present invention relate generally to logic devices, and more particularly, to magnetoelectric magnetic tunneling junction computational devices. Aspects of the disclosed technology include a stand-alone voltage-controlled magnetoelectric device that satisfies essential requirements for general logic applications, including nonlinearity, gain, concatenability, feedback prevention, and a complete set of Boolean operations based on the majority gate and inverter. Aspects of the present disclosed technology can eliminate the need for any auxiliary FETs to preset or complicated clocking schemes, and prevents the racing condition. ## Claims ### Claim 1 A semiconductor device, comprising: an input electrode and a ground electrode configured to produce an electric field within a layer of antiferromagnetic material when a voltage is applied to the input electrode relative to the ground electrode, wherein the layer of antiferromagnetic material produces a magnetic field in response to the application of an electric field; a first free magnet and a second free magnet, wherein the first and second free magnet are separated by a first isolation layer, wherein the first free magnet is in magnetic communication with the layer of antiferromagnetic material, and wherein the second free magnet is magnetically coupled to the first free magnet; a permanent magnet in contact with a second isolation layer, wherein the second isolation layer is in contact with the second free magnet; a digital voltage electrode in electrical communication with the first permanent magnet; and an output electrode in electrical communication with the second free magnet. ### Claim 2 (depends on 1) The semiconductor device of claim 1, further comprising: a second permanent magnet in contact with a third isolation layer, wherein the third isolation layer is in contact with the second free magnet; and a second digital voltage electrode in electrical communication with the second permanent magnet, wherein a magnetoresistance between the first digital electrode and ground is different than a magnetoresistance between the second digital electrode and ground depending on the magnetic orientation of the permanent magnets. ### Claim 3 (depends on 2) The semiconductor device of claim 2, wherein a voltage applied to the second digital voltage electrode has a substantially equal magnitude and opposite polarity as the voltage applied to the digital voltage electrode relative to ground. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein the input electrode is in electrical communication with the antiferromagnetic layer, and wherein the ground electrode is in electrical communication with the first free magnet. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein the input electrode is in electrical communication with the first free magnet, and wherein the ground electrode is in electrical communication with the antiferromagnetic layer. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein the second free magnet is coupled to the first free magnet by exchange coupling. ### Claim 7 (depends on 1) The semiconductor device of claim 1, wherein the second free magnet is coupled to the first free magnet by dipole coupling. ### Claim 8 (depends on 1) The semiconductor device of claim 1, further comprising a second input electrode, wherein the second electrode is configured to produce an electric field within the layer of antiferromagnetic material when a voltage is applied to the second input electrode relative to the ground electrode. ### Claim 9 (depends on 1) The semiconductor device of claim 1, wherein the first isolation layer has a thickness selected to suppress leakage current from the digital voltage electrode to the ground electrode. ### Claim 10 (depends on 1) The semiconductor device of claim 1, wherein the first second isolation layer has a thickness selected to permit electron tunneling between the digital voltage electrode and the output electrode when the polarity of the first permanent magnet and the second free magnet are similarly directed. ### Claim 11 (depends on 1) The semiconductor device of claim 1, wherein a thickness of the first isolation layer is approximately two times to three times a thickness of the first second isolation layer. ### Claim 12 (depends on 1) The semiconductor device of claim 1, wherein the permanent magnet comprises a layer comprised, at least in part, of an alloy of cobalt and iron, and a layer comprised, at least in part, of an alloy of iridium and magnesium. ### Claim 13 (depends on 1) The semiconductor device of claim 1, wherein the antiferromagnetic layer comprises a material selected from the group of: chromium oxide, bismuth ferrite, and combinations thereof. ### Claim 14 (depends on 1) The semiconductor device of claim 1, wherein the first free magnet comprises a material selected from the group of cobalt iron alloys, cobalt palladium alloys, lanthanum strontium manganite, and combinations thereof. ### Claim 15 (depends on 1) The semiconductor device of claim 1, wherein the first isolation layer comprises a material selected from the group of: magnesium oxide, yttrium-aluminum-garnet, iron oxide, and combinations thereof. ### Claim 16 (depends on 1) The semiconductor device of claim 1, wherein the second isolation layer comprises a material selected from the group of: magnesium oxide, aluminum oxide, and combinations thereof. ### Claim 17 A semiconductor device, comprising: a first logic gate comprising, an input electrode and a ground electrode configured to produce an electric field within a layer of antiferromagnetic material when a voltage is applied to the input electrode relative to the ground electrode, wherein the layer of antiferromagnetic material produces a magnetic field in response to the application of an electric field, a first free magnet and a second free magnet, wherein the first and second free magnet are separated by a first isolation layer, wherein the first free magnet is in magnetic communication with the layer of antiferromagnetic material, and wherein the second free magnet is magnetically coupled to the first free magnet, a permanent magnet in contact with a second isolation layer, wherein the second isolation layer is in contact with the second free magnet, a digital voltage electrode in electrical communication with the first permanent magnet, and an output electrode in electrical communication with the second free magnet; and a second logic gate, comprising: an input electrode and a ground electrode configured to produce an electric field within a layer of antiferromagnetic material when a voltage is applied to the input electrode relative to the ground electrode, wherein the layer of antiferromagnetic material produces a magnetic field in response to the application of an electric field, a first free magnet and a second free magnet, wherein the first and second free magnet are separated by a first isolation layer, wherein the first free magnet is in magnetic communication with the layer of antiferromagnetic material, and wherein the second free magnet is magnetically coupled to the first free magnet, a permanent magnet in contact with a second isolation layer, wherein the second isolation layer is in contact with the second free magnet, and a digital voltage electrode in electrical communication with the first permanent magnet; and an output electrode in electrical communication with the second free magnet; wherein the input electrode of the first logic device is in electrical communication with the antiferromagnetic layer of the first logic device, and the ground electrode of the first logic is in electrical contact with the first free magnet of the first logic device; wherein the input electrode of the second logic device is in electrical communication with the first free magnet of the second logic device, and the ground electrode of the second logic device is in electrical contact with the antiferromagnetic layer of the second logic device; and wherein the output electrode of the first logic device is in electrical communication with the output electrode of the second logic device. ### Claim 18 A semiconductor device, comprising: a logic component, comprising: an input electrode and a ground electrode configured to produce an electric field within a layer of antiferromagnetic material that produces a magnetic field in response to the application of an electric field, a free magnet and a permanent magnet, wherein the free magnet and permanent magnet are separated by a magnet isolation layer, wherein the free magnet is in magnetic communication with the layer of antiferromagnetic material and an output electrode in electric communication with the permanent magnet; a bias component, comprising: a first pre-set electrode and a second pre-set electrode configured to produce an electric field within a layer of antiferromagnetic material that produces a magnetic field in response to the application of an electric field, a free magnet and a permanent magnet, wherein the free magnet and the permanent magnet are separated by a magnet isolation layer, wherein the free magnet is in magnetic communication with the layer of antiferromagnetic material, and an output electrode in electric communication with the permanent magnet, wherein the output electrode of the bias component is in electrical communication with the output electrode of the logic component; wherein the logic component is configured to be pre-set by applying a ground voltage to the first pre-set electrode and a pre-set voltage to the second pre-set electrode; wherein the logic component is configured to be operable by applying an operating voltage to the second pre-set electrode, and a voltage approximately double the operating voltage to the first pre-set electrode, wherein the operating voltage has an opposite polarity from the pre-set voltage. ### Claim 19 (depends on 18) The semiconductor device of claim 18, wherein the permanent magnet and free magnet of the bias component have parallel polarities. ### Claim 20 (depends on 18) The semiconductor device of claim 18, wherein pre-setting the logic component comprises magnetizing the first free magnet of the logic component. ### Claim 21 (depends on 18) The semiconductor device of claim 18, wherein the logic component of the semiconductor device further comprises a second input electrode configured to produce an electric field within the layer of antiferromagnetic material of the logic component when a voltage is applied to the second input electrode relative to ground. ### Claim 22 (depends on 18) The semiconductor device of claim 18, wherein the input electrode of the logic component is in electric communication with the free magnet of the logic component, and wherein the ground electrode of the logic component is in electric communication with the antiferromagnetic layer of the logic component. ### Claim 23 (depends on 18) The semiconductor device of claim 18, wherein input electrode of the logic component is in electric communication with the antiferromagnetic layer of the logic component, and wherein the ground electrode of the logic component is in electric communication with the free magnet of the logic component. ### Claim 24 (depends on 18) The semiconductor device of claim 18, wherein the magnet isolation layer of the logic component and the magnet isolation layer of the bias component are composed of a material selected to have a high electrical resistivity. ### Claim 25 (depends on 19) The semiconductor device of claim 19, wherein the operating voltage is selected to bias the free magnet of the logic component to have a polarity opposite to the polarization of the permanent magnet of the logic component present when no input is applied to the logic component.