# US 2018/0026641 A1 · FPGA RAM Blocks Optimized for Use as Register Files > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0026641 A1 - Document ID: US20180026641A1 - Status: Published application - Kind: A1 - Application number: 15/713,952 - Filed: 2017-09-25 - Published: 2018-01-25 - Earliest claimed: 2011-05-05 - Assignees: Microsemi SoC Corporation - Applicants: Microsemi SoC Corporation - Inventors: Joel Landry; Jonathan Greene; William C. Plants; Wenyi Feng - Web page: https://patentgrep.com/patent/US20180026641A1 ## CPC - H03K 19/177: arranged in matrix form - G11C 8/16: Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups - H03K 19/1776: for memories - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array with logic modules and routing interconnects programmably coupleable to the logic modules and the RAM circuit. The RAM circuit has three ports: a first readable port, a second readable port, and a writeable port. The read ports may be programmably synchronous or asynchronous and have a programmably bypassable output pipeline register. The RAM circuit is especially well adapted for implementing register files. A novel interconnect method is also described. ## Claims ### Claim at position 1 1-7. (canceled) ### Claim 8 A field programmable gate array integrated circuit device comprising: a programmable array having logic modules and routing interconnects programmably coupleable to the logic modules; a random-access memory circuit including first, second, and third ports, at least two of the first second, and third ports comprising a plurality of address input terminals and a plurality of data output terminals; a plurality of address input nodes associated with the random-access memory circuit, each address input node programmably coupleable to the routing interconnects; a plurality of data output nodes associated with the random-access memory circuit, each data output node programmably coupleable to the routing interconnects; an address clocked logic element associated with each of the address input nodes, each address clocked logic element having a data input coupled to a different one of the address input nodes, a clock input, and a data output; and a plurality of address input multiplexers, each address input multiplexer having a first data input coupled to the output of a different one of the address clocked input address input nodes, a second data input coupled to a different one of the address input nodes, a data output coupled to a different one of the address input terminals, and a select input. ### Claim 9 (depends on 8) The field programmable gate array integrated circuit device of claim 8, wherein the select input of each address input multiplexer is programmably controlled. ### Claim 10 (depends on 9) The field programmable gate array integrated circuit device of claim 9, wherein the select inputs of all of the address input multiplexers are programmably controlled together. ### Claim 11 (depends on 8) The field programmable gate array integrated circuit device of claim 8, wherein each address clocked logic element associated with the address input nodes comprises a flip-flop. ### Claim 12 (depends on 8) The field programmable gate array integrated circuit device of claim 8, wherein each address clocked logic element associated with the address input nodes includes a read-enable input coupled to a source of a read enable signal. ### Claim 13 (depends on 12) The field programmable gate array integrated circuit device of claim 12, wherein the source of the read enable signal for each address clocked logic element associated with the address input nodes has programmable polarity. ### Claim 14 (depends on 8) The field programmable gate array integrated circuit device of claim 8, wherein the clock input of each address clocked logic element associated with the address input nodes is coupled to a source of a read clock signal. ### Claim 15 (depends on 14) The field programmable gate array integrated circuit device of claim 14, wherein the source of the read clock signal for each address clocked logic element associated with the address input nodes has programmable polarity. ### Claim 16 (depends on 8) The field programmable gate array integrated circuit device of claim 8, further comprising: a data clocked logic element associated with each of the data output nodes, each data clocked logic element having a data input coupled to a different one of the data output terminals, a clock input, and a data output coupled to a different one of the data output nodes; and a plurality of data output multiplexers, each data output multiplexer having a first data input coupled to the output of a different one of the data clocked logic elements, a second data input coupled to a different one of the data output terminals, a data output coupled to a different one of the data output nodes, and a select input. ### Claim 17 (depends on 16) The field programmable gate array integrated circuit device of claim 16, wherein the select input of each data output multiplexer is programmably controlled. ### Claim 18 (depends on 17) The field programmable gate array integrated circuit device of claim 17, wherein the select inputs of all of the data output multiplexers are programmably controlled together. ### Claim 19 (depends on 16) The field programmable gate array integrated circuit device of claim 16, wherein each address clocked logic element associated with the data output nodes comprises a flip-flop. ### Claim 20 (depends on 16) The field programmable gate array integrated circuit device of claim 16, wherein each data clocked logic element associated with the data output nodes includes a read-enable input coupled to a source of a read enable signal. ### Claim 21 (depends on 20) The field programmable gate array integrated circuit device of claim 20, wherein the source of the read enable signal for each of the data clocked logic elements associated with the data output nodes has programmable polarity. ### Claim 22 (depends on 16) The field programmable gate array integrated circuit device of claim 16, wherein the clock input of each data clocked logic element associated with the data output nodes is coupled to a source of a read clock signal. ### Claim 23 (depends on 14) The field programmable gate array integrated circuit device of claim 14, wherein the source of the read clock signal for each data clocked logic element associated with the data output nodes has programmable polarity.