# US 2018/0026631 A1 · Biasing scheme for high voltage circuits using low voltage devices

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- Number: US 2018/0026631 A1
- Document ID: US20180026631A1
- Status: Published application
- Kind: A1
- Application number: 15/714,672
- Filed: 2017-09-25
- Published: 2018-01-25
- Earliest claimed: 2014-12-05
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Mayank Goel; Prasad Bhilawadi; Karthik Ns
- Web page: https://patentgrep.com/patent/US20180026631A1

## CPC

- H03K 17/687: the devices being field-effect transistors
- H03K 17/165: {by feedback from the output circuit to the control circuit}
- H03K 2217/0027: Measuring means of, e.g. currents through or voltages across the switch
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

Some embodiments include apparatus and methods having a first node to receive a supply voltage, a second node to receive a first bias voltage, a third node to receive ground potential, a first circuit branch coupled between the first and second nodes, and a second circuit branch coupled between the first and third nodes. The first bias voltage is provided to a gate of a first transistor among a plurality of transistors coupled in series. The first and second circuit branches are arranged to provide a second bias voltage to gate of a second transistor among the plurality of transistors. The value of the second bias voltage is based on a value of the first bias voltage.

## Claims

### Claim at position 1

1-15. (canceled)

### Claim 16

An apparatus comprising:
an integrated circuit including a first node to receive a supply voltage and a second node to receive ground potential; and
a transmitter located in the integrated circuit, the transmitter including a buffer to transmit a signal, the buffer including:
an output stage including a first pair of transistors coupled between the first node and an output node, and a second pair of transistors coupled between the output node and the second node; and
a bias stage to provide a first bias voltage to a gate of a transistor in the second pair of transistors and a second bias voltage to a gate of a transistor in the first pair of transistors, wherein a value of each of the first and second bias voltages is greater than zero, and the value of the second bias voltage is based on a value of the supply voltage and the value of the first bias voltage.

### Claim 17 (depends on 16)

The apparatus of claim 16, wherein the value of the second bias voltage is based. on a difference between the value of the supply voltage and the value of the first bias voltage.

### Claim 18 (depends on 16)

The apparatus of claim 16, wherein the output node is arranged to couple to a connector, the connector including at least one of a Secure Digital Input Output (SDIO) connector, a MultiMediaCard (MMC) connector, a Universal Serial Bus (USB) connector, and a Subscriber Identity Module (SIM) connector.

### Claim 19 (depends on 16)

The apparatus of claim 16, further comprising at least one of a display coupled to the integrated circuit and an antenna coupled to the integrated circuit.

### Claim 20 (depends on 16)

The apparatus of claim 16, wherein the apparatus comprises a system on a chip (SoC), and the output node is part of an input/output (I/O) pad of the SoC.

### Claim 21 (depends on 16)

The apparatus of claim 16, further comprising a pre-driver to provide a signal to a gate of a transistor in the first pair of transistors, wherein the signal has a signal swing between a level based on a value of the first voltage and a level based on the value of the second bias voltage.

### Claim 22 (depends on 21)

The apparatus of claim 21, further comprising an additional pre-driver to provide an additional signal to a gate of a transistor in the second pair of transistors, wherein the additional signal has a signal swing between a level based on a value of the second voltage and a level based on the value of the first bias voltage.

### Claim 23 (depends on 16)

The apparatus of claim 16, further comprising a third node to receive the first bias voltage, wherein the bias stage includes a bias voltage generator to generate the second bias voltage at an output of the bias voltage generator, the bias voltage generator including a first circuit branch having a first circuit portion coupled between the first and third nodes, and a second circuit branch having a second circuit portion coupled between the first and second nodes, and wherein the first and second circuit portions have matched circuit structure, and the value of the second bias voltage is a function of a current and a resistance across the second circuit portion.

### Claim 24 (depends on 23)

The apparatus of claim 23, wherein the bias voltage generator further comprising a third circuit branch coupled between the first and second nodes and arranged with the first and second circuit branches such that the second bias voltage is provided at a node in the third circuit branch.

### Claim 25 (depends on 24)

The apparatus of claim 24, further comprising:
first additional transistors coupled between the first node and the output of the bias voltage generator, the first additional transistors arranged to operate as an inverter having an input to receive a first input signal and an output to provide the first signal based on the first input signal; and
second additional transistors coupled between the second node and the gate of the first transistor of the output stage, the second additional transistors arranged to operate as an inverter having an input to receive a second input signal and an output to provide the second signal based on the second input signal.

### Claim 26 (depends on 16)

The apparatus of claim 16, wherein the first node is arranged to receive the first voltage including a supply voltage having a range from approximately 2.7 volts to approximately 3.6 volts.

### Claim 27 (depends on 26)

The apparatus of claim 26, further comprising a third node to receive an additional supply voltage having a value of approximately 1.8 volts, wherein the first bias voltage has a value based on the value of the additional supply voltage.

### Claim 28

An apparatus comprising:
an integrated circuit including a first node to receive a first voltage and a second node to receive a second voltage; and
a transmitter located in the integrated circuit, the transmitter including a circuit to transmit a signal, the circuit including:
a first stage including a first pair of transistors of a first transistor type coupled between the first node and an output node, and a second pair of transistors of a second transistor type coupled between the output node and the second node; and
a second stage to provide a first bias voltage to a gate of a transistor in the second pair of transistors and a second bias voltage to a gate of a first transistor in the first pair of transistors, wherein a value of each of the first and second bias voltages is greater than zero, and the value of the second bias voltage is based on the value of the first voltage and the value of the first bias voltage.

### Claim 29 (depends on 28)

The apparatus of claim 28, wherein the first voltage includes a supply voltage of the apparatus, the second voltage includes ground potential.

### Claim 30 (depends on 28)

The apparatus of claim 28, wherein the first pair of transistors include p-channel field effect transistors, and the second pair of transistors include n-channel field effect transistors.

### Claim 31 (depends on 28)

The apparatus of claim 28, further comprising a pre-driver to provide a signal to a gate of a transistor in the first pair of transistors.

### Claim 32 (depends on 31)

The apparatus of claim 31, further comprising an additional pre-driver to provide an additional signal to a gate of a transistor in the second pair of transistors.

### Claim 33 (depends on 32)

The apparatus of claim 32, wherein:
the pre-driver includes a pair of transistor coupled between the first node and a node that provides the second bias voltage; and
the additional pre-driver includes a pair of transistor coupled between the second node and a node that provides the first bias voltage;

### Claim 34 (depends on 32)

The apparatus of claim 32, wherein the signal provided to the gate of the transistor in the first pair of transistors has a signal swing between a level based on a value of the first voltage and a level based on the value of the second bias voltage.

### Claim 35 (depends on 33)

The apparatus of claim 33, wherein the additional signal provided to the gate of the transistor in the second pair of transistors has a signal swing between a level based on a value of the second voltage and a level based on the value of the first bias voltage.