# US 2018/0026630 A1 · Circuit with transistors having coupled gates

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- Number: US 2018/0026630 A1
- Document ID: US20180026630A1
- Status: Published application
- Kind: A1
- Application number: 15/215,310
- Filed: 2016-07-20
- Published: 2018-01-25
- Earliest claimed: 2016-07-20
- Assignees: Semiconductor Components Industries, LLC
- Applicants: Semiconductor Components Industries, LLC
- Inventors: Jaume ROIG-GUITART; Balaji PADMANABHAN; Prasad VENKATRAMAN
- Web page: https://patentgrep.com/patent/US20180026630A1

## CPC

- H03K 17/165: {by feedback from the output circuit to the control circuit}
- H03K 2217/0036: Means reducing energy consumption
- H03K 2217/0054: Gating switches, e.g. pass gates
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A circuit can include a first transistor including a source and a gate; a second transistor including a drain and a gate, wherein the source of the first transistor is coupled to the drain of the second transistor; and a switchable element. In one embodiment, a first current-carrying terminal of the switchable element is coupled to the gate of the first transistor, and a second current-carrying terminal of the switchable element is coupled to the gate of the second transistor. In another embodiment, the switchable element is coupled to the gate of the first transistor and includes a first selectable terminal of the switchable element coupled to a source of the second transistor, and a second selectable terminal of the switchable element coupled to the gate of the second transistor. In a particular embodiment, the circuit can be a cascode circuit

## Claims

### Claim 1

A circuit comprising:
a first transistor including a source and a gate;
a second transistor including a drain and a gate, wherein the source of the first transistor is coupled to the drain of the second transistor; and
a switchable element including a first current-carrying terminal and a second current carrying terminal, wherein the first current-carrying terminal of the switchable element is coupled to the gate of the first transistor, and the second current-carrying terminal of the switchable element is coupled to the gate of the second transistor.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein the switchable element includes a third transistor that is a field-effect transistor.

### Claim 3 (depends on 2)

The circuit of claim 2, wherein the third transistor is a depletion-mode transistor.

### Claim 4 (depends on 2)

The circuit of claim 2, wherein the third transistor is a MISFET.

### Claim 5 (depends on 2)

The circuit of claim 2, wherein the first current-carrying terminal of the switchable element is a drain of the third transistor, and the second current-carrying terminal of the switchable element is a source of the third transistor.

### Claim 6 (depends on 2)

The circuit of claim 2, wherein the third transistor further includes a gate coupled to the source of the second transistor.

### Claim 7 (depends on 2)

The circuit of claim 2, wherein the third transistor further includes a gate coupled to the source of the first transistor and the drain of the second transistor.

### Claim 8 (depends on 2)

The circuit of claim 2, wherein the third transistor further includes a gate coupled to a switch controller outside the cascode circuit.

### Claim 9 (depends on 2)

The circuit of claim 2, wherein the first transistor is a depletion-mode transistor, and the second transistor is an enhancement-mode transistor.

### Claim 10 (depends on 9)

The circuit of claim 9, wherein:
the first transistor is a depletion-mode GaN HEMT;
the second transistor is an enhancement-mode Si MISFET; and
the third transistor is a depletion-mode Si MISFET or GaN HEMT.

### Claim 11 (depends on 10)

The circuit of claim 10, wherein a gate of the third transistor is electrically connected to the source of the second transistor.

### Claim 12 (depends on 10)

The circuit of claim 10, wherein a gate of the third transistor is electrically connected to the source of the first transistor and the drain of the second transistor.

### Claim 13 (depends on 1)

The circuit of claim 1, further comprising a first passive component coupled between the second current-carrying terminal of the switchable element and a control terminal of the cascode circuit or the gate of the second transistor.

### Claim 14 (depends on 13)

The circuit of claim 13, further comprising a second passive component, wherein:
the first passive component is coupled between the second current-carrying terminal of the switchable element and the control terminal of the cascode circuit; and
the second passive component is coupled between the second current-carrying terminal of the switchable element and the gate of the second transistor.

### Claim 15 (depends on 14)

The circuit of claim 14, wherein the first passive component is a first resistor having a first resistance, the second passive component is a second resistor having a second resistance that is greater than the first resistance.

### Claim 16 (depends on 14)

The circuit of claim 14, wherein a substrate of the first transistor is coupled to the source of the second transistor.

### Claim 17

A circuit comprising:
a first transistor including a source and a gate;
a second transistor including a drain, a source, and a gate, wherein the source of the first transistor is coupled to the drain of the second transistor; and
a switchable element coupled to the gate of the first transistor and including a first selectable terminal and a second selectable terminal, wherein the first selectable terminal of the switchable element is coupled to the source of the second transistor, and the second selectable terminal of the switchable element is coupled to the gate of the second transistor.

### Claim 18 (depends on 17)

The circuit of claim 17, wherein the electronic device is configured such that in a first state, the gate of the first transistor is coupled to first selectable terminal, and in a second state, the gate of the first transistor is coupled to the second selectable terminal.

### Claim 19 (depends on 18)

The circuit of claim 18, wherein the first transistor is a depletion-mode, and the second transistor is an enhancement-mode transistor.

### Claim 20 (depends on 19)

The circuit of claim 19, wherein the first transistor is a GaN HEMT, and the second transistor is a Si transistor.