# US 2018/0026622 A1 · Apparatuses and methods for reducing off state leakage currents > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0026622 A1 - Document ID: US20180026622A1 - Status: Published application - Kind: A1 - Application number: 15/217,449 - Filed: 2016-07-22 - Published: 2018-01-25 - Earliest claimed: 2016-07-22 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: PIERGUIDO GAROFALO - Web page: https://patentgrep.com/patent/US20180026622A1 ## CPC - H03K 17/063: {in field-effect transistor switches} - G11C 7/08: Control thereof - G11C 7/1063: {Control signal output circuits, e.g. status or busy flags, feedback command signals} - G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating - H03K 17/6874: {in a symmetrical configuration} - H03K 19/0013: {in field effect transistor circuits} - G11C 2207/2245: Memory devices with an internal cache buffer - H03K 2217/0036: Means reducing energy consumption - H03K 2217/0054: Gating switches, e.g. pass gates - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Apparatuses and methods for reducing leakage currents during an off state for transistors are described herein. An example apparatus includes a switch having an input node and an output node. The switch is configured to couple a signal on the input to the output node when the switch is in an on state and is further configured to decouple the input and output nodes when the switch is in an off state. The switch includes first and second transistors, and further includes third and fourth transistors. A drain electrode of the first transistor is coupled to a source electrode of the third transistor, a drain electrode of the second transistor is coupled to a source electrode of the fourth transistor, and the drain electrodes of the third and fourth transistors are coupled together to the output node. ## Claims ### Claim 1 An apparatus, comprising: a switch having an input node and an output node, wherein the switch is configured to couple a signal on the input node to the output node when the switch is in an on state and further configured to decouple the input and output nodes when the switch is in an off state, and wherein the switch comprises: first and second transistors, each having gate, source and drain electrodes, wherein the first and second transistors are configured to be in an off state when the switch is in the off state based on a high reference voltage coupled to the gate of the first transistor and a low reference voltage coupled to the gate of the second transistor; and third and fourth transistors, each having gate, source and drain electrodes, wherein the third and fourth transistors are configured to be in a first conductive state when the switch is in the off state based on an intermediate voltage coupled to the gates of the third and fourth transistors, wherein the intermediate voltage is less than the high reference voltage and greater than the low reference voltage, wherein the third and fourth transistors are configured to be in a second conductive state when the switch is in the on state based on the low reference voltage coupled to the gate of the third transistor and the high reference voltage coupled to the gate of the fourth transistor, wherein the drain electrode of the first transistor is coupled to the source electrode of the third transistor, the drain electrode of the second transistor is coupled to the source electrode of the fourth transistor, and wherein the drain electrodes of the third and fourth transistors are coupled together to the output node. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein source electrodes of the first and second transistors are coupled together to the input node, and wherein gate electrodes of the first and second transistors are selectively provided a low reference voltage and a high reference voltage, respectively, to cause the first and second transistors to be in the off state. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the first and second transistors form a pass gate. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the third and fourth transistors are cascode coupled with the first and second transistors, respectively. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the source electrodes of the first and second transistors are coupled to high and low reference voltages, respectively, and gate electrodes of the first and second transistors are selectively provided a low reference voltage and a high reference voltage, respectively, to cause the first and second transistors to be in the off state. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the first, second, third and fourth transistors form a first high impedance inverter. ### Claim 7 (depends on 6) The apparatus of claim 6, further comprising: an inverter having an input and an output, wherein the input of the inverter is coupled to the input node; a second high impedance inverter having an input and an output, wherein the input is coupled to the output of the inverter; a voltage source coupled to the gates of the third and fourth transistors, wherein the voltage source is configured to provide the intermediate voltage when the switch is in the off state, and further configured to be in a high impedance state when the switch is in the on state, and wherein the gates of the third and fourth are further coupled to the output of the second high impedance inverter. ### Claim 8 A switch, comprising: a first pass gate comprising a first PMOS transistor and a first NMOS transistor, wherein a source electrode of the first PMOS transistor is coupled to an input of the first pass gate, and a source electrode of the first NMOS transistor is coupled to the input of the first pass gate, a drain electrode of the first PMOS transistor is coupled to a first intermediate node, and a drain electrode of the first NMOS transistor is coupled to a second intermediate node, and wherein, when the switch is in the off state, a gate electrode of the first PMOS transistor is selectively provided a first reference voltage and a gate electrode of the first NMOS transistor is selectively provided a second reference voltage; and a second pass gate comprising a second PMOS transistor and a second NMOS transistor, wherein a source electrode of the second PMOS transistor is coupled to the first intermediate node, and a source of the second NMOS transistor is coupled to the second intermediate node, and drain electrodes of the second PMOS and NMOS transistors are coupled to an output of the second pass gate, and wherein, when the switch is in the off state, gate electrodes of the second PMOS and NMOS transistors are selectively provided a third reference voltage, wherein the third reference voltage is less than the first reference voltage and greater than the second reference voltage, wherein, when the switch is in the on state, the gate electrode of the second NMOS transistor is selectively provided the first reference voltage and the gate electrode of the second PMOS transistor is selectively provided the second reference voltage. ### Claim 9 (depends on 8) The switch of claim 8, wherein the second pass gate is cascode coupled to the first pass gate. ### Claim 10 (depends on 8) The switch of claim 8, wherein the first pass gate is in an on state when the gate electrode of the first PMOS transistor is coupled to a low reference voltage, and the gate electrode of the first NMOS transistor is coupled to a high reference voltage. ### Claim 11 (depends on 8) The switch of claim 8, wherein the second reference voltage is equal to the low reference voltage, and the second reference voltage is equal to to the high reference voltage. ### Claim 12 (depends on 11) The switch of claim 11, wherein the switch is in the on state when both the first and second pass gates are in the on state. ### Claim 13 (canceled) ### Claim 14 (canceled) ### Claim 15 (canceled) ### Claim 16 An apparatus, comprising: a voltage source configured to provide an intermediate reference voltage or be in a high impedance state based on a control signal; a first high impedance inverter having an input and an output, and further having an enable input and a not enable input, wherein the first high impedance inverter is in an off state or an on state based on a voltage coupled to the enable and not enable inputs; and a second high impedance inverter coupled to the first high impedance inverter and the voltage source at an input, wherein the second high impedance inverter comprises: a first transistor having a gate, a source and a drain electrode, wherein the source electrode is coupled to a high reference voltage, and the gate electrode is coupled to a low or high reference voltage based on an operational state of the second high impedance inverter; a second transistor having a gate, a source and a drain electrode, wherein the source electrode is coupled to the drain electrode of the first transistor, and wherein the gate electrode is coupled to the output of the first high impedance amplifier and further coupled to the voltage source; a third transistor having a gate, a source and a drain electrode, wherein the drain electrode is coupled to the drain electrode of the second transistor, wherein the gate electrode is coupled to the output of the first high impedance amplifier and further coupled to the voltage source, and wherein the drain electrodes of the second and third transistors are coupled to the output of the second high impedance inverter; and a fourth transistor having a source, a drain, and a gate electrode, wherein the drain electrode of the fourth transistor is coupled to the source electrode of the third transistor, and the source electrode is coupled to a low reference voltage, and wherein the gate electrode is coupled to the low or high reference voltage based on an operational state of the second high impedance inverter. ### Claim 17 (depends on 16) The apparatus of claim 16, wherein the first high impedance amplifier is in the on state when the not enable input is coupled to a low reference voltage and the enable input is coupled to a high reference voltage input. ### Claim 18 (depends on 16) The apparatus of claim 16, further comprising an inverter having an input and an output, wherein the input of the inverter is coupled to an input node, and wherein the output of the inverter is coupled to the input of the first high impedance inverter. ### Claim 19 (depends on 16) The apparatus of claim 16, wherein the second high impedance inverter is in an on state when the gate electrode of the first transistor is coupled to a low reference voltage, the gate electrode of the fourth transistor is coupled to a high reference voltage, and the voltage source is in a high impedance state. ### Claim 20 (depends on 16) The apparatus of claim 16, wherein the second high impedance inverter is in an off state when the gate electrode of the first transistor is coupled to a high reference voltage, the gate electrode of the fourth transistor is coupled to a low reference voltage, and the voltage source is providing the intermediate reference voltage to the gate electrodes of the second and third transistors. ### Claim 21 (depends on 19) The apparatus of claim 19, wherein the second and third transistors are in a conductive state when the second high impedance inverter is in an off state.