# US 2018/0026620 A1 · Overvoltage protection circuit

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2018/0026620 A1
- Document ID: US20180026620A1
- Status: Published application
- Kind: A1
- Application number: 15/723,491
- Filed: 2017-10-03
- Published: 2018-01-25
- Earliest claimed: 2013-03-15
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Daniel M. Dreps
- Web page: https://patentgrep.com/patent/US20180026620A1

## CPC

- H03K 17/04: Modifications for accelerating switching
- G06F 13/4072: {Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002)}
- H02H 3/20: responsive to excess voltage
- H03K 17/0822: {in field-effect transistor switches}
- H03K 17/687: the devices being field-effect transistors
- H05K 3/303: with surface mounted components (H05K3/32 takes precedence)
- H05K 3/32: electrically connecting electric components or wires to printed circuits
- G06F 2213/0042: Universal serial bus [USB]
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H)
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

## Abstract

Universal Serial Bus (USB) protection circuits are provided. A circuit includes a plurality of first transistors connected in series between a pad and ground. The circuit also includes a plurality of second transistors connected in series between the pad and a supply voltage. The circuit further includes a control circuit that applies respective bias voltages to each one of the plurality of first transistors and to each one of the plurality of second transistors. The bias voltages are configured to: turn off the plurality of first transistors and turn off the plurality of second transistors when a pad voltage of the pad is within a nominal voltage range; sequentially turn on the plurality of first transistors when the pad voltage increases above the nominal voltage range; and sequentially turn on the plurality of second transistors when the pad voltage decreases below the nominal voltage range.

## Claims

### Claim 1

A circuit, comprising:
a first PFET and a second PFET connected in series between a pad having a pad voltage and ground;
a first NFET and a second NFET connected in series between the pad and a supply voltage;
a third PFET, wherein a source of the third PFET is connected to a gate of the first PFET, and the pad voltage is applied to a gate of the third PFET; and
a third NFET, wherein a source of the third NFET is connected to a gate of the first NFET, and the pad voltage is applied to a gate of the third NFET.

### Claim 2 (depends on 1)

The circuit of claim 1, further comprising:
a first voltage divider connected to the gate of the first PFET; and
a second voltage divider connected to the gate of the first NFET.

### Claim 3 (depends on 2)

The circuit of claim 2, further comprising:
a first resistance element connected between a drain of the second PFET and ground; and
a second resistance element connected between a drain of the second NFET and the supply voltage.

### Claim 4 (depends on 1)

The circuit of claim 1, further comprising:
a first bias voltage applied to the gate of the first PFET;
a second bias voltage, less than the first bias voltage, applied to the gate of the second PFET;
a third bias voltage applied to the gate of the first NFET; and
a fourth bias voltage, less than the third bias voltage, applied to the gate of the second NFET.

### Claim 5 (depends on 4)

The circuit of claim 4, wherein:
the first bias voltage is an output of a first voltage divider; and
the third bias voltage is an output of a second voltage divider.

### Claim 6

A circuit, comprising:
a first PFET and a second PFET connected in series between a pad having a pad voltage and ground;
a first NFET and a second NFET connected in series between the pad and a supply voltage;
a third PFET, wherein a source of the third PFET is connected to a gate of the first PFET, and the pad voltage is applied to a gate of the third PFET; and
a third NFET, wherein a source of the third NFET is connected to a gate of the first NFET, and the pad voltage is applied to a gate of the third NFET,
wherein a drain of the third PFET is connected to a gate of the second PFET; and
a drain of the third NFET is connected to a gate of the second NFET.

### Claim 7 (depends on 6)

The circuit of claim 6, further comprising:
a first resistance element connected between a drain of the second PFET and ground; and
a second resistance element connected between a drain of the second NFET and the supply voltage.

### Claim 8 (depends on 6)

The circuit of claim 6, further comprising:
a first voltage divider connected to the gate of the first PFET; and
a second voltage divider connected to the gate of the first NFET.

### Claim 9 (depends on 6)

The circuit of claim 6, further comprising:
a first bias voltage applied to the gate of the first PFET;
a second bias voltage, less than the first bias voltage, applied to the gate of the second PFET;
a third bias voltage applied to the gate of the first NFET; and
a fourth bias voltage, less than the third bias voltage, applied to the gate of the second NFET.

### Claim 10 (depends on 9)

The circuit of claim 9, wherein:
the first bias voltage is an output of a first voltage divider; and
the third bias voltage is an output of a second voltage divider.

### Claim 11

A circuit, comprising:
a first PFET and a second PFET connected in series between a pad having a pad voltage and ground;
a first NFET and a second NFET connected in series between the pad and a supply voltage;
a third PFET, wherein a source of the third PFET is connected to a gate of the first PFET, and the pad voltage is applied to a gate of the third PFET; and
a third NFET, wherein a source of the third NFET is connected to a gate of the first NFET, and the pad voltage is applied to a gate of the third NFET,
wherein a drain of the third PFET is connected to a drain of the first PFET and a source of the second PFET; and
a drain of the third NFET is connected to a drain of the first NFET and a source of the second NFET.

### Claim 12 (depends on 11)

The circuit of claim 11, further comprising:
a first resistance element connected between a drain of the second PFET and ground; and
a second resistance element connected between a drain of the second NFET and the supply voltage.

### Claim 13 (depends on 11)

The circuit of claim 11, further comprising:
a first voltage divider connected to the gate of the first PFET; and
a second voltage divider connected to the gate of the first NFET.

### Claim 14 (depends on 11)

The circuit of claim 11, further comprising:
a first bias voltage applied to the gate of the first PFET;
a second bias voltage, less than the first bias voltage, applied to the gate of the second PFET;
a third bias voltage applied to the gate of the first NFET; and
a fourth bias voltage, less than the third bias voltage, applied to the gate of the second NFET.

### Claim 15 (depends on 14)

The circuit of claim 14, wherein:
the first bias voltage is an output of a first voltage divider; and
the third bias voltage is an output of a second voltage divider.