# US 2018/0026616 A1 · Input device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0026616 A1 - Document ID: US20180026616A1 - Status: Published application - Kind: A1 - Application number: 15/656,107 - Filed: 2017-07-21 - Published: 2018-01-25 - Earliest claimed: 2016-07-22 - Assignees: Thine Electronics, Inc. - Applicants: Thine Electronics, Inc. - Inventors: Yutaka CHIBA - Web page: https://patentgrep.com/patent/US20180026616A1 ## CPC - H03K 5/24: the characteristic being amplitude - H03K 5/2472: {using field effect transistors (H03K5/2436 takes precedence)} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract The embodiment relates to an input device comprises first and second MOS transistors, first to fourth resistors, and a comparator circuit. The first MOS transistor has a drain connected to a first terminal having a first voltage, a gate connected to a signal input terminal, and a source connected to a second terminal having a second voltage via the first and third resistors. The second MOS transistor has a drain and a gate connected to the first terminal, and a source connected to the second terminal via the second and fourth resistors. The comparator circuit outputs a signal having a level corresponding to a state in which a voltage of a node between the first and third resistors is higher or lower than a voltage of a node between the second and fourth resistors. ## Claims ### Claim 1 An input device comprising: a first reference terminal set at a first reference voltage; a second reference terminal set at a second reference voltage; a signal input terminal configured to receive an input signal; a signal output terminal configured to output a signal having a level corresponding to a state in which a voltage value of the input signal is higher or lower than a predetermined threshold value; a first MOS transistor having a drain electrically connected to the first reference terminal, a gate electrically connected to the signal input terminal, and a source; a second MOS transistor having a drain and a gate electrically connected to the first reference terminal, and a source; a first resistor having one end electrically connected to the source of the first MOS transistor, and the other end electrically connected to a first node; a second resistor having one end electrically connected to the source of the second MOS transistor, and the other end electrically connected to a second node; a third resistor having one end electrically connected to the first node, and the other end electrically connected to the second reference terminal; a fourth resistor having one end electrically connected to the second node, and the other end electrically connected to the second reference terminal; and a comparator circuit having a first input terminal electrically connected to the first node and set at the same voltage as the first node, a second input terminal electrically connected to the second node and set at the same voltage as the second node, and an output terminal, which is the signal output terminal, configured to output a signal having a level corresponding to a state in which a voltage of the first input terminal is higher or lower than a voltage of the second input terminal. ### Claim 2 (depends on 1) The input device according to claim 1, wherein a resistance value of the third resistor is equal to a resistance value of the fourth resistor. ### Claim 3 (depends on 1) The input device according to claim 1, wherein a resistance value of the third resistor is more than ten times larger than a resistance value of the first resistor, and a resistance value of the fourth resistor is more than 10 times larger than a resistance value of the second resistor. ### Claim 4 (depends on 2) The input device according to claim 2, wherein the resistance value of the third resistor is more than ten times larger than a resistance value of the first resistor, and the resistance value of the fourth resistor is more than 10 times larger than a resistance value of the second resistor. ### Claim 5 (depends on 1) The input device according to claim 1, further comprising a fifth resistor having one end electrically connected to the first reference terminal, and the other end electrically connected to the drain of the second MOS transistor. ### Claim 6 (depends on 5) The input device according to claim 5, wherein the sum of a resistance value of the second resistor and a resistance value of the fifth resistor is equal to a resistance value of the first resistor. ### Claim 7 An input device comprising: a first reference terminal set at a first reference voltage; a second reference terminal set at a second reference voltage; a signal input terminal configured to receive an input signal; a signal output terminal configured to output a signal having a level corresponding to a state in which a voltage value of the input signal is higher or lower than a predetermined threshold value; a first MOS transistor having a drain electrically connected to the first reference terminal, a gate electrically connected to the signal input terminal, and a source; a second MOS transistor having a drain and a gate electrically connected to the first reference terminal, and a source; a first resistor having one end electrically connected to the source of the first MOS transistor, and the other end electrically connected to a first node; a second resistor having one end electrically connected to the source of the second MOS transistor, and the other end electrically connected to a second node; a first current source having one end electrically connected to the first node, and the other end electrically connected to the second reference terminal; a second current source having one end electrically connected to the second node, and the other end electrically connected to the second reference terminal; and a comparator circuit having a first input terminal electrically connected to the first node and set at the same voltage as the first node, a second input terminal electrically connected to the second node and set at the same voltage as the second node, and an output terminal, which is the signal output terminal, configured to output a signal having a level corresponding to a state in which a voltage of the first input terminal is higher or lower than a voltage of the second input terminal. ### Claim 8 (depends on 7) The input device according to claim 7, wherein a current flowing through the first current source is equal to a current flowing through the second current source. ### Claim 9 (depends on 7) The input device according to claim 7, further comprising a fifth resistor having one end electrically connected to the first reference terminal, and the other end electrically connected to the drain of the second MOS transistor. ### Claim 10 (depends on 9) The input device according to claim 9, wherein the sum of a resistance value of the second resistor and a resistance value of the fifth resistor is equal to a resistance value of the first resistor.