# US 2018/0026613 A1 · Balancing delay associated with dual-edge trigger clock gaters

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- Number: US 2018/0026613 A1
- Document ID: US20180026613A1
- Status: Published application
- Kind: A1
- Application number: 15/217,122
- Filed: 2016-07-22
- Published: 2018-01-25
- Earliest claimed: 2016-07-22
- Assignees: Apple Inc.
- Applicants: Apple Inc.
- Inventors: Victor Zyuban; Norman Rohrer; Nimish Kabe; Neela Lohith Penmetsa
- Web page: https://patentgrep.com/patent/US20180026613A1

## CPC

- H03K 5/05: by the use of clock signals or other time reference signals
- H03K 3/037: Bistable circuits
- H03K 5/131: Digitally controlled
- H03K 19/0016: {by using a control or a clock signal, e.g. in order to apply power supply}
- H03K 19/21: EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

Techniques are disclosed relating to dual-edge triggered (DET) clock gater circuitry. In some embodiments, an apparatus includes a first series of DET clock gater circuits configured, when the DET clock gater circuits are not gating an input clock signal, to provide an output clock signal to sequential circuitry. In some embodiments, ones of the DET clock gater circuits are controlled by respective control signals and are configured to maintain a mode indicator indicating whether or not the DET clock gater circuit is inverting the polarity of its input clock when generating an output clock. In some embodiments, the apparatus also includes a first adjustable delay circuit configured to adjust delay imposed on the output clock signal from the first series of DET clock gater circuits based on the number of DET clock gater circuits in the series that are in a particular mode.

## Claims

### Claim 1

An apparatus, comprising:
a first series of dual-edge triggered (DET) clock gater circuits configured, when the DET clock gater circuits are not gating an input clock signal, to provide an output clock signal to sequential circuitry, wherein ones of the DET clock gater circuits are controlled by respective control signals and wherein ones of the DET clock gater circuits are configured to maintain a mode indicator indicating whether or not the DET clock gater circuit is inverting the polarity of its input clock when generating an output clock; and
a first adjustable delay circuit configured to adjust delay imposed on the output clock signal from the first series of DET clock gater circuits based on the number of DET clock gater circuits in the series that are in a particular mode.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein ones of the DET clock gaters are configured to switch between inverting and non-inverting modes based on whether prior clock gating lasted an even or odd number of clock edges.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the first adjustable delay circuit includes an inverter and wherein the apparatus is configured to adjust an amount of current provided to the inverter to adjust the delay imposed on the output clock signal.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the apparatus is configured to determine the mode of a DET clock gater circuit based on an output of a storage element included in the DET clock gater circuit.

### Claim 5 (depends on 1)

The apparatus of claim 1, further comprising:
a second series of DET clock gater circuits configured, when the DET clock gater circuits are not gating an input clock signal, to provide an output clock signal to sequential circuitry; and
a second adjustable delay circuit configured to adjust delay imposed on the output clock signal from the second series of DET clock gater circuits based on the number of DET clock gater circuits in the second series that are in a particular mode; and
control circuitry configured to control delay adjustments by the first adjustable delay circuit and the second adjustable delay circuit such that a clock delay of the series and the second series matches.

### Claim 6 (depends on 1)

The apparatus of claim 1, further comprising:
control circuitry configured to adjust delay imposed by the first adjustable delay circuit in response to determining that a threshold number of DET clock gater circuits in the series that are in the particular mode.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the first adjustable delay circuit is configured to both increase and reduce delay asserted, at different times based on input control signals, relative to a nominal imposed delay.

### Claim 8

A method, comprising:
providing a clock signal to sequential circuitry via a first series of dual-edge triggered (DET) clock gater circuits;
determining respective modes of the DET clock gater circuits, wherein the mode indicates whether or not the DET clock gater circuit is inverting the polarity of its input clock when generating an output clock signal; and
adjusting delay asserted by an adjustable delay circuit coupled to delay the clock signal output from the first series of DET clock gater circuits.

### Claim 9 (depends on 8)

The method of claim 8, wherein ones of the DET clock gater circuits switch between inverting and non-inverting modes based on whether clock gating lasts an even or odd number of clock edges.

### Claim 10 (depends on 8)

The method of claim 8, wherein the adjusting delay includes adjusting an amount of current provided to one or more inverters.

### Claim 11 (depends on 8)

The method of claim 8, wherein the adjusting delay includes enabling or disabling one or more inverters.

### Claim 12 (depends on 8)

The method of claim 8, wherein the determining respective modes is based on an output of a storage element included in ones of the DET clock gater circuits.

### Claim 13 (depends on 8)

The method of claim 8, further comprising:
providing a second clock signal to sequential circuitry via a second series of DET clock gater circuits;
determining respective modes of the second series of DET clock gater circuits; and
adjusting delay asserted by a second adjustable delay circuit coupled to delay the clock signal output from the second series of DET clock gater circuits, wherein the adjusting is performed to match the delays of the first and second series of DET clock gater circuits.

### Claim 14 (depends on 8)

The method of claim 8, wherein the adjusting the delay asserted by the adjustable delay circuit is performed in response to determining that a threshold number of DET clock gater circuits in the series that are in a particular mode.

### Claim 15 (depends on 8)

The method of claim 8, wherein the adjusting includes increasing delay asserted by the adjustable delay circuit, relative to a nominal delay, during a first interval and reducing delay asserted by the adjustable delay circuit, relative to the nominal delay, during a second interval.

### Claim 16

A non-transitory computer readable storage medium having stored thereon design information that specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the circuit according to the design, including:
a first series of dual-edge triggered (DET) clock gater circuits configured, when the DET clock gater circuits are not gating an input clock signal, to provide an output clock signal to sequential circuitry, wherein ones of the DET clock gater circuits are controlled by respective control signals and wherein ones of the DET clock gater circuits are configured to maintain a mode indicator indicating whether or not the DET clock gater circuit is inverting the polarity of its input clock when generating an output clock; and
a first adjustable delay circuit configured to adjust delay imposed on the output clock signal from the first series of DET clock gater circuits based on the number of DET clock gater circuits in the series that are in a particular mode.

### Claim 17 (depends on 16)

The non-transitory computer readable storage medium of claim 16, wherein ones of the DET clock gaters are configured to switch between inverting and non-inverting modes based on whether prior clock gating lasted an even or odd number of clock edges.

### Claim 18 (depends on 16)

The non-transitory computer readable storage medium of claim 16, wherein the design information specifies that the first adjustable delay circuit includes an inverter and that the circuit is configured to adjust an amount of current provided to the inverter to adjust the delay imposed on the output clock signal.

### Claim 19 (depends on 16)

The non-transitory computer readable storage medium of claim 16, wherein the design information further specifies that the circuit includes:
a second series of DET clock gater circuits configured, when the DET clock gater circuits are not gating an input clock signal, to provide an output clock signal to sequential circuitry; and
a second adjustable delay circuit configured to adjust delay imposed on the output clock signal from the second series of DET clock gater circuits based on the number of DET clock gater circuits in the second series that are in a particular mode; and
control circuitry configured to control delay adjustments by the first adjustable delay circuit and the second adjustable delay circuit such that a clock delay of the series and the second series matches.

### Claim 20 (depends on 16)

The non-transitory computer readable storage medium of claim 16, wherein the mode indicator is based on a comparison of input and output clock signals for a given one of the DET clock gater circuits and indicates a first mode if the polarity if the input and output clock signals are the same and indicates a second mode if the polarity of the input and output clock signals are different.