# US 2018/0026438 A1 · Embedded battery protection system

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- Number: US 2018/0026438 A1
- Document ID: US20180026438A1
- Status: Published application
- Kind: A1
- Application number: 15/722,823
- Filed: 2017-10-02
- Published: 2018-01-25
- Earliest claimed: 2015-04-03
- Assignees: Shanghai SIM-BCD Semiconductor Manufacturing Co., Ltd.; BCD Semiconductor Manufacturing Limited
- Applicants: Shanghai Sim-Bcd Semiconductor Manufacturing Co., Ltd.; Bcd Semiconductor Manufacturing Limited
- Inventors: SHAOHUA PENG; Xuguang Zhang
- Web page: https://patentgrep.com/patent/US20180026438A1

## CPC

- H02H 7/18: for batteries; for accumulators
- H02J 7/60: including safety or protection arrangements
- G06F 1/263: {Arrangements for using multiple switchable power supplies, e.g. battery and AC (G06F1/30 takes precedence)}
- G06F 1/30: Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations (for resetting only G06F1/24)
- H02J 7/663: {using battery or load disconnect circuits (H02J9/002 takes precedence)}
- H04W 88/02: Terminal devices
- H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H)
- H02J: ELECTRIC POWER NETWORKS; CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04W: WIRELESS COMMUNICATION NETWORKS (broadcast communication H04H; communication systems using wireless links for non-selective communication, e.g. wireless extensions H04M1/72)

## Abstract

A signal processing circuit includes a first circuit coupled between a power terminal and a first ground terminal and a second circuit coupled between the power terminal and a second ground terminal. The signal processing circuit is configured to receive a first signal at a voltage level relative to the first ground terminal and, in response to the first signal, provide a second signal at a voltage level relative to the second ground terminal. The signal processing circuit can be used in a battery protection circuit for a mobile device having an embedded battery. The battery protection circuit is configured with two NMOS transistors to allow the cell phone circuit to switch between the embedded battery and an external power source.

## Claims

### Claim 1

A battery control circuit for a mobile device, wherein the mobile device has an embedded battery and is configured for coupling to an external power source, the battery control circuit comprising:
first and second high-voltage NMOS transistors coupled in series and configured for connecting between a ground terminal of the embedded battery in the mobile device and a ground terminal of the external power source; and
a battery protection IC (integrated circuit) including:
a power terminal for coupling to a power terminal of the embedded battery and a power terminal of the external power supply;
a first ground terminal for coupling to the ground terminal of the external power source; and
a second ground terminal for coupling to the ground terminal of the embedded battery;
wherein the battery protection IC is configured to:
receive a signal from a functional block in the mobile device, the signal having a voltage level relative to the ground terminal of the external power source;
and
in response to the signal, provide one or more control signals having voltage levels relative to the ground terminal of the embedded battery, the control signals being configured to turn on the first and the second high-voltage NMOS transistors to connect the embedded battery to the functional block in mobile device, or to turn off the first and the second high-voltage NMOS transistors to disconnect the embedded battery from the functional block in the mobile device.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein the battery protection IC comprises:
a signal processing circuit configured to receive an input signal having a voltage level relative to the first ground terminal and to provide an output signal having a voltage level relative to the second ground terminal in response to the input signal; and
a logic circuit coupled to the signal processing circuit and configured to provide one or more control signals having voltage levels relative to the second ground terminal in response to the output signal of the signal processing circuit.

### Claim 3 (depends on 2)

The circuit of claim 2, wherein the signal processing circuit comprises:
a first circuit coupled between the power terminal and the first ground terminal, the first circuit being configured to receive an input signal having a voltage level relative to the first ground terminal and to provide first and second complementary digital signals in response to the input signal; and
a second circuit coupled between the power terminal and the second ground terminal, the second circuit being configured to provide a digital output signal relative to the second ground terminal in response to the first and second complementary digital signals.

### Claim 4 (depends on 3)

The circuit of claim 3, wherein the first circuit comprises:
an input stage having an enhancement-mode NMOS transistor and a depletion-mode NMOS transistor coupled in series at a first internal node between the power terminal and the first ground terminal, a gate of the enhancement-mode NMOS transistor configured to receive the input signal;
a Schmitt trigger coupled to the input stage at the first node and configured to provide the first and second complementary digital signals; and
an inverter circuit coupled to an output of the Schmitt trigger to provide the second complementary digital signal.

### Claim 5 (depends on 3)

The circuit of claim 3, wherein the second circuit comprises:
a first PMOS transistor and a first NMOS transistor coupled in series between the power terminal and the second ground terminal;
a second PMOS transistor and a second NMOS transistor coupled in series between the power terminal and the first ground terminal;
wherein the first and second NMOS transistors are cross-coupled at the gate and drain terminals;
the first and the second PMOS transistors are configured to receive the first and second complementary digital signals from the first circuit; and
a node between the second PMOS transistor and the second NMOS transistor is configured to provide the digital output signal relative to the second ground terminal.

### Claim 6 (depends on 2)

The circuit of claim 2, wherein the logic circuit is configured to provide first and second control signals to turn on and off first and second high-voltage NMOS transistors in response to the output signal of the signal processing circuit.

### Claim 7 (depends on 1)

The circuit of claim 1, wherein the first high-voltage NMOS transistor comprises a source and a substrate coupled to the second ground terminal, and the second high-voltage NMOS transistor comprises a source and a substrate coupled to the first ground terminal.

### Claim 8 (depends on 1)

The circuit of claim 1, wherein the first ground terminal of the battery protection IC is coupled to the ground terminal of the external power source through a current-limiting resistor.

### Claim 9 (depends on 1)

The signal processing circuit of claim 1, wherein the signal processing circuit is configured to receive a first control signal at a voltage level relative to the first ground terminal and, in response to the first control signal, provide a second control signal at a voltage level relative to the second ground terminal to connect the first ground terminal and the second ground terminal, when the first ground terminal and the second ground terminal are electrically disconnected from each other.

### Claim 10

A control circuit, comprising:
a power terminal;
first and second ground terminals;
a signal processing circuit including:
a first circuit coupled between the power terminal and the first ground terminal; and
a second circuit coupled between the power terminal and the second ground terminal,
wherein the signal processing circuit is configured to receive a first signal at a voltage level relative to the first ground terminal and, in response to the first signal, provide a second signal at a voltage level relative to the second ground terminal; and
a logic circuit coupled between the power terminal and the second ground terminal, the logic circuit being configured to receive the second signal and to provide one or more output signals at voltage levels relative to the second ground terminal in response to the second control signal.

### Claim 11 (depends on 10)

The control circuit of claim 10, wherein
the first circuit is configured to receive an input signal having a voltage level relative to the first ground terminal and to provide first and second complementary digital signals in response to the input signal; and
the second circuit is configured to provide a digital output signal relative to the second ground terminal in response to the first and second complementary digital signals.

### Claim 12 (depends on 11)

The control circuit of claim 11, wherein the first circuit comprises:
an input stage having an enhancement-mode NMOS transistor and a depletion-mode NMOS transistor coupled in series at a first internal node between the power terminal and the first ground terminal, a gate of the enhancement-mode NMOS transistor configured to receive the input signal;
a Schmitt trigger coupled to the input stage at the first node; and
an inverter circuit coupled to an output of the Schmitt trigger to provide the first and second complementary digital signals.

### Claim 13 (depends on 11)

The control circuit of claim 11, wherein the second circuit comprises:
a first PMOS transistor and a first NMOS transistor coupled in series between the power terminal and the second ground terminal;
a second PMOS transistor and a second NMOS transistor coupled in series between the power terminal and the second ground terminal;
wherein the first and second NMOS transistors are cross-coupled at the gate and drain terminals;
the first and the second PMOS transistors are configured to receive the first and second complementary digital signals from the first circuit; and
a node between the second PMOS transistor and the second NMOS transistor is configured to provide the digital output signal relative to the second ground terminal.

### Claim 14 (depends on 10)

The control circuit of claim 10, wherein the one or more output signals are configured to turn on a switch device between the first ground terminal to the second ground terminal to connect the first ground terminal to the second ground terminal, even when the second ground terminal is electrically floating relative to the first ground terminal.

### Claim 15

A signal processing circuit, comprising:
a first circuit coupled between a power terminal and a first ground terminal; and
a second circuit coupled between the power terminal and a second ground terminal;
wherein the signal processing circuit is configured to receive a first signal at a voltage level relative to the first ground terminal and, in response to the first signal, provide a second signal at a voltage level relative to the second ground terminal.

### Claim 16 (depends on 15)

The signal processing circuit of claim 15, wherein
the first circuit is configured to receive an input signal having a voltage level relative to the first ground terminal and to provide first and second complementary digital signals in response to the input signal; and
the second circuit is configured to provide a digital output signal relative to the second ground terminal in response to the first and second complementary digital signals.

### Claim 17 (depends on 16)

The signal processing circuit of claim 16, wherein the first circuit comprises:
an input stage having an enhancement-mode NMOS transistor and a depletion-mode NMOS transistor coupled in series at a first internal node between the power terminal and the first ground terminal, a gate of the enhancement-mode NMOS transistor configured to receive the input signal;
a Schmitt trigger coupled to the input stage at the first node; and
an inverter circuit coupled to an output of the Schmitt trigger to provide the first and second complementary digital signals.

### Claim 18 (depends on 15)

The control circuit of claim 15, wherein the second circuit comprises:
a first PMOS transistor and a first NMOS transistor coupled in series between the power terminal and the second ground terminal;
a second PMOS transistor and a second NMOS transistor coupled in series between the power terminal and the first ground terminal;
wherein the first and second NMOS transistors are cross-coupled at the gate and drain terminals;
the first and the second PMOS transistors are configured to receive the first and second complementary digital signals from the first circuit; and
a node between the second PMOS transistor and the second NMOS transistor is configured to provide the digital output signal relative to the second ground terminal.