# US 2018/0026134 A1 · Semiconductor device and method of manufacturing the same

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- Number: US 2018/0026134 A1
- Document ID: US20180026134A1
- Status: Published application
- Kind: A1
- Application number: 15/649,984
- Filed: 2017-07-14
- Published: 2018-01-25
- Earliest claimed: 2016-07-20
- Assignees: Renesas Electronics Corporation
- Applicants: Renesas Electronics Corporation
- Inventors: Katsumi EIKYU; Atsushi SAKAI
- Web page: https://patentgrep.com/patent/US20180026134A1

## CPC

- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/6717: {the source and the drain regions being asymmetrical}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 64/01312: {the additional layer comprising a metal or metal silicide formed by deposition, i.e. without a silicidation reaction, e.g. sputter deposition}
- H10D 64/111: {Field plates}
- H10D 64/311: {Gate electrodes for field-effect devices}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 64/671: {the conductor having lateral variation in doping or structure}
- H10D 64/675: {Gate sidewall spacers}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

In an LDMOS having an element isolation region of an STI structure, there is prevented an occurrence of insulation breakdown which might be caused when electrons generated in a semiconductor substrate near an edge portion of a bottom face of the element isolation region are poured into a gate electrode. Immediately over an upper surface of an offset region adjacent to the element isolation region embedded in a main surface of the semiconductor substrate between a source region and a drain region, there is provided a trench penetrating a silicon film forming the gate electrode. As a consequence, the silicon film and a metal film for filling the trench form the gate electrode.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor substrate;
a source region and a drain region being formed over an upper surface of the semiconductor substrate and each being of p conductive type;
a gate electrode formed over the semiconductor substrate between the source region and the drain region through a gate insulating film; and
a first insulating film embedded in a trench formed, in a gate-length direction of the gate electrode, over the upper surface of the semiconductor substrate between the gate insulating film and the drain region,
wherein part of the gate electrode is formed immediately above the first insulating film, and
wherein the gate electrode includes:
a semiconductor film; and
a metal film which is embedded in a second trench penetrating the semiconductor film immediately above the upper surface of the semiconductor substrate between the first insulating film and the source region and is electrically coupled to the semiconductor film.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein part of the metal film in the second trench is located immediately above the first insulating film.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein a sidewall is formed which includes a second insulating film for covering a side surface of the second trench.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein a third insulating film is interposed between the metal film and the gate insulating film in the second trench.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4, wherein the third insulating film covers a bottom face and a side surface of the second trench and its film thickness is smaller than that of the gate insulating film.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, further including a first p type semiconductor region electrically coupled to the drain region and formed ranging from a bottom face of the first trench over the upper surface of the semiconductor substrate closer to the source region side than the first trench,
wherein p type impurity concentration of the first p type semiconductor region is lower than p type impurity concentration of the drain region, and
wherein the second trench is formed immediately above an upper surface of the first p type semiconductor region adjacent to the first insulating film.

### Claim 7 (depends on 6)

The semiconductor device according to claim 6,
wherein the drain region and the first p type semiconductor region are electrically coupled through a second p type semiconductor region formed in the semiconductor substrate, and
wherein p type impurity concentration of the second p type semiconductor region is lower than p type impurity concentration of the drain region and higher than p type impurity concentration of the first p type semiconductor region.

### Claim 8 (depends on 3)

The semiconductor device according to claim 3 further including a first p type semiconductor region electrically coupled to the drain region and formed ranging from a bottom face of the first trench over the upper surface of the semiconductor substrate closer to the source region side than the first trench side,
wherein p type impurity concentration of the first p type semiconductor region is lower than p type impurity concentration of the drain region, and
wherein part of the semiconductor film located closer to the source region side than the metal film is located immediately above the first p type semiconductor region.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1, wherein the first insulating film has an STI structure.

### Claim 10

A semiconductor device, comprising:
a semiconductor substrate;
a source region and a drain region being formed over an upper surface of the semiconductor substrate and each being of p conductive type;
a gate electrode formed over the semiconductor substrate between the source region and the drain region through a gate insulating film; and
a first insulating film embedded in a trench formed over the upper surface of the semiconductor substrate between the gate insulating film and the drain region in a gate-length direction of the gate electrode,
wherein part of the gate electrode is formed immediately above the first insulating film, and
wherein the gate electrode includes:
a metal film located immediately above the upper surface of the semiconductor substrate between the first insulating film and the source region; and
a semiconductor film electrically coupled to the metal film and located between the metal film and the source region in the gate-length direction.

### Claim 11

A method of manufacturing a semiconductor device, comprising the steps of:
(a) providing a semiconductor substrate;
(b) forming a source region of p conductive type and a drain region of p conductive type over an upper surface of the semiconductor substrate;
(c) forming a first trench in the upper surface of the semiconductor substrate and forming a first insulating film embedded in the first trench;
(d) forming a gate insulating film covering the upper surface of the semiconductor substrate between the first insulating film and the source region;
(e) after the step (d), forming a semiconductor film immediately above the first insulating film between the source region and the drain region and immediately above the upper surface of the semiconductor substrate between the first insulating film and the source region;
(f) exposing the upper surface of the semiconductor substrate between the first insulating film and the source region from the semiconductor film by forming a second trench penetrating the semiconductor film; and
(g) forming a gate electrode including a metal film and the semiconductor film by forming the metal film filling the second trench,
wherein the gate electrode, the source region, and the drain region form a field-effect transistor.

### Claim 12 (depends on 11)

The method of manufacturing a semiconductor device according to claim 11, further comprising a step of:
(f1) after the step (f) but before the step (g), forming a sidewall including a second insulating film covering a side surface of the second trench.

### Claim 13 (depends on 11)

The method of manufacturing a semiconductor device according to claim 11, further comprising a step of:
(f2) after the step (f) but before the step (g), forming a third insulating film covering a bottom face of the second trench.

### Claim 14 (depends on 13)

The method of manufacturing a semiconductor device according to claim 13, wherein the third insulating film covers a bottom face and a side surface of the second trench and its film thickness is smaller than that of the gate insulating film.

### Claim 15 (depends on 11)

The method of manufacturing a semiconductor device according to claim 11, further comprising a step of:
(a1) after the step (a) but before the step (d), forming a p type semiconductor region over an upper surface of the semiconductor substrate,
wherein, after the step (f), the p type semiconductor region is formed from a bottom face of the first trench over the upper surface of the semiconductor substrate closer to the source region side than the first trench,
wherein p type impurity concentration of the p type semiconductor region is lower than p type impurity concentration of the drain region, and
wherein the second trench is formed immediately above an upper surface of the p type semiconductor region.