# US 2018/0026129 A1 · Trench Edge Termination Structure for Power Semiconductor Devices

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- Number: US 2018/0026129 A1
- Document ID: US20180026129A1
- Status: Published application
- Kind: A1
- Application number: 15/602,122
- Filed: 2017-05-23
- Published: 2018-01-25
- Earliest claimed: 2016-07-25
- Assignees: University of Electronic Science and Technology of China
- Applicants: University of Electronic Science and Technology of China
- Inventors: Min REN; Chi XIE; Jiaju LI; Ziqi ZHONG; Zehong LI; Jinping ZHANG; Wei GAO; Bo ZHANG
- Web page: https://patentgrep.com/patent/US20180026129A1

## CPC

- H10D 30/665: {having edge termination structures}
- H10D 62/103: {for increasing or controlling the breakdown voltage of reverse-biased devices}
- H10D 62/104: {having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats}
- H10D 62/112: {for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/124: {Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions}
- H10D 62/364: {of IGFETs}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/115: {Resistive field plates, e.g. semi-insulating field plates}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10P 50/642: {Chemical etching}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Edge termination structures for power semiconductor devices (or power devices) are disclosed. The purpose of this invention is to reduce the difficulty of deep trench etching and dielectric filling by adopting an inverted trapezoidal trench. In order to save the area of edge termination and get a high blocking voltage on condition that the angle between the sidewall of the trench and horizontal is large, fixed charges are introduced at a particular location in the trench. Due to the Coulomb interaction between the ionized impurity in the drift region and the fixed charges, the depletion region of the terminal PN junction can extend fully, which relieves the concentration of electric field there. Therefore, the edge termination can exhibit a high breakdown voltage near to that of the parallel plane junction with a smaller area and the reduced technical difficulty of deep trench etching and dielectric filling.

## Claims

### Claim 1

A trench termination structure of a power semiconductor device, comprising:
a heavily doped P-type substrate;
a lightly doped P-type drift region on an upper surface of the heavily doped P-type substrate;
a metal drain electrode on a lower surface of the heavily doped P-type substrate; and
a field oxide layer on an upper surface of the lightly doped P-type drift region,
wherein the lightly doped P-type drift region includes a trench and a heavily doped P-type region;
the heavily doped P-type region is located in a top portion of the lightly doped P-type drift region and on a side away from an active region of the power semiconductor device;
an upper surface of the heavily doped P-type region contacts a lower surface of the field oxide layer;
the trench is filled with an insulating material whose upper surface contacts a lower surface of the field oxide layer;
a polysilicon floating island that stores positive charges is located in the trench;
a sidewall of the trench on a side near the active region contacts a N-type semiconductor main junction;
an upper surface of the polysilicon floating island is lower than a lower surface of the N-type semiconductor main junction;
a cross-sectional shape of the trench is an inverted trapezium; and
an angle between the sidewall and a horizontal plane is in the range of 60 to 90 degrees.

### Claim 2

A trench termination structure of a power semiconductor device, comprising:
a heavily doped N-type substrate;
a lightly doped N-type drift region on an upper surface of the heavily doped N-type substrate;
a metal drain electrode on a lower surface of the heavily doped N-type substrate; and
a field oxide layer on an upper surface of the lightly doped N-type drift region,
wherein
the lightly doped N-type drill region includes a trench and a heavily doped N-type region;
the heavily doped N-type region is located in a top portion of the lightly doped N-type drift region and on a side away from an active region of the power semiconductor device;
an upper surface of the heavily doped N-type region contacts a lower surface of the field oxide layer;
the trench is filled with an insulating material whose upper surface contacts a lower surface of the field oxide layer:
a polysilicon floating island that stores negative charges is located in the trench;
a sidewall of the trench on a side near the active region contacts a P-type semiconductor main junction;
an upper surface of the polysilicon floating island is lower than a lower surface of the P-type semiconductor main junction;
a cross-sectional shape of the trench is an inverted trapezium: and
an angle between the sidewall and a horizontal plane is in the range of 60 to 90 degrees.