# US 2018/0026128 A1 · High acceptor level doping in silicon germanium

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- Number: US 2018/0026128 A1
- Document ID: US20180026128A1
- Status: Published application
- Kind: A1
- Application number: 15/668,357
- Filed: 2017-08-03
- Published: 2018-01-25
- Earliest claimed: 2016-07-20
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Mona Abdulkhaleg Ebrish; Oleg Gluschenkov; Shogo Mochizuki; Alexander Reznicek
- Web page: https://patentgrep.com/patent/US20180026128A1

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0241: {doping of vertical sidewalls, e.g. using tilted or multi-angled implants}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/834: further characterised by the dopants
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 30/20: into semiconductor materials, e.g. for doping
- H10P 32/1408: {from or through or into an external applied layer, e.g. photoresist or nitride layers}
- H10P 32/171: {being group IV material}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure is provided in which gallium-doped sacrificial epitaxial or polycrystalline germanium layer is formed on a silicon germanium substrate having a high percentage of germanium followed by annealing to diffuse the gallium into the silicon germanium substrate. The germanium layer is selectively removed to expose the surface of a gallium-doped silicon germanium region within the silicon germanium substrate. The process has application to the formation of electrically conductive regions within integrated circuits such as source/drain regions and junctions without the introduction of carbon into such regions.

## Claims

### Claim 1

A semiconductor structure comprising:
a substrate including a silicon germanium alloy surface layer having the composition Si1-xGex where x is 0.85 or greater;
a gallium-doped silicon germanium region within the silicon germanium alloy surface layer, the gallium-doped silicon germanium region having a dopant profile comprising a diffusion profile and including no dopant-induced end-of-range crystal defects.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the gallium-doped silicon germanium region has a gallium concentration of at least 2×1020 cm−3.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein the gallium-doped silicon germanium region is essentially carbon-free.

### Claim 4 (depends on 3)

The semiconductor structure of claim 3, wherein the silicon germanium alloy surface layer comprises a plurality of parallel fins.

### Claim 5 (depends on 3)

The semiconductor structure of claim 3, wherein the gallium-doped silicon germanium region of the silicon germanium alloy surface layer comprises a source/drain region of a field-effect transistor.

### Claim 6 (depends on 5)

The semiconductor structure of claim 5, wherein the silicon germanium alloy surface layer comprises epitaxial regions extending from a semiconductor fin.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein the silicon germanium alloy surface layer comprises an extension of a source/drain region of a field-effect transistor.