# US 2018/0026067 A1 · Complementary metal-oxide-semiconductor (cmos) image sensor (cis) package with an image buffer

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- Number: US 2018/0026067 A1
- Document ID: US20180026067A1
- Status: Published application
- Kind: A1
- Application number: 15/216,815
- Filed: 2016-07-22
- Published: 2018-01-25
- Earliest claimed: 2016-07-22
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Hsiao-Wen Lee; Kazuaki Hashimoto; Kuo-Chung Yee
- Web page: https://patentgrep.com/patent/US20180026067A1

## CPC

- H10F 39/809: {of hybrid image sensors}
- H10F 39/018: {of hybrid image sensors}
- H10F 39/18: Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
- H10F 39/811: {Interconnections}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 72/073: {of die-attach connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) package is provided. The image sensor package comprises a first integrated circuit (IC) die, a second IC die, and a fan-out structure. The first IC die comprises a pixel sensor array, and the second IC die is under and bonded to the first IC die. Further, the fan-out structure is under and bonded to the second IC die. The fan-out structure comprises a third IC die, a fan-out dielectric layer laterally adjacent to the third IC die, a through insulator via (TIV) extending through the fan-out dielectric layer, and one or more redistribution layers (RDLs) under the third IC die and the TIV. The one or more RDLs electrically couple to the third IC die and the TIV. A method for manufacturing the CIS package is also provided.

## Claims

### Claim 1

An image sensor package comprising:
a first integrated circuit (IC) die comprising a pixel sensor array;
a second IC die under and bonded to the first IC die;
an interface layer between the first IC die and the second IC die, wherein the interface layer is configured to bond and electrically couple the second IC die to the first IC die at an insulator-to-insulator interface and a metal-to-metal interface, and wherein the metal-to-metal interface is even with the insulator-to-insulator interface; and
a fan-out structure under and bonded to the second IC die, wherein the fan-out structure comprises:
a third IC die;
a fan-out dielectric layer laterally adjacent to the third IC die;
a through insulator via (TIV) extending through the fan-out dielectric layer; and
one or more redistribution layers (RDLs) under the third IC die and the TIV, wherein the one or more RDLs electrically couple to the third IC die and the TIV.

### Claim 2

An image sensor package comprising:
a first integrated circuit (IC) die comprising a pixel sensor array;
a second IC die under and bonded to the first IC die; and
a fan-out structure under and bonded to the second IC die, wherein the fan-out structure comprises:
a third IC die;
a fan-out dielectric layer laterally adjacent to the third IC die;
a through insulator via (TIV) extending through the fan-out dielectric layer; and
one or more redistribution layers (RDLs) under the third IC die and the TIV, wherein the one or more RDLs electrically couple to the third IC die and the TIV;
wherein the second IC die comprises:
a semiconductor substrate along a bottom of the second IC die; and
a through substrate via (TSV) extending through the semiconductor substrate, from the bottom of the second IC die, wherein the TSV is aligned and electrically coupled to the TIV.

### Claim 3 (depends on 2)

The image sensor package according to claim 2, wherein the TSV extends from the bottom of the second IC die to a top of the second IC die.

### Claim 4 (depends on 2)

The image sensor package according to claim 2, wherein the second IC die comprises an interconnect structure over the semiconductor substrate, and wherein the TSV terminates at a bottom of the interconnect structure.

### Claim 5 (depends on 1)

The image sensor package according to claim 1, further comprising:
an interface layer between the second IC die and the fan-out structure, wherein the interface layer is configured to bond and electrically couple the second IC die to the fan-out structure at an insulator-to-insulator interface and a metal-to-metal interface, and wherein the metal-to-metal interface is even with the insulator-to-insulator interface.

### Claim 6 (depends on 1)

The image sensor package according to claim 1, wherein sidewalls of the fan-out structure are aligned to sidewalls of the second IC die and to sidewalls of the first IC die.

### Claim 7 (depends on 1)

The image sensor package according to claim 1, wherein the second IC die is configured as an image signal processor (ISP) and the third IC die is configured as dynamic random-access memory (DRAM).

### Claim 8 (depends on 1)

The image sensor package according to claim 1, wherein the second IC die is configured as dynamic random-access memory (DRAM) and the third IC die is configured as an image signal processor (ISP).

### Claim 9 (depends on 1)

The image sensor package according to claim 1, wherein the fan-out structure comprises a fourth IC die arranged laterally adjacent to the third IC die.

### Claim at position 10

10-20. (canceled)

### Claim 21

An image sensor package comprising:
a first integrated circuit (IC) die comprising a pixel sensor array and a first interconnect layer, wherein the first interconnect layer is electrically coupled to and underlies the pixel sensor array;
a second IC die under the first IC die, wherein the second IC die is bonded and electrically coupled to the first IC die, and wherein the second IC die comprises:
a semiconductor substrate along a bottom of the second IC die; and
a pair of through substrate vias (TSVs) extending through the semiconductor substrate from the bottom of the second IC die; and
a fan-out structure under and bonded to the second IC die, wherein the fan-out structure comprises:
a fan-out dielectric layer;
a third IC die over the fan-out dielectric layer, wherein the third IC die is recessed into the fan-out dielectric layer such that a top surface of the third IC die is even with a top surface of the fan-out dielectric layer;
a pair of through insulator vias (TIV) extending through the fan-out dielectric layer, wherein the TIVs are on opposite sides of the third IC die, and wherein the TIVs are aligned and electrically coupled to the TSVs, respectively; and
one or more redistribution layers (RDLs) under the third IC die and the TIVs, wherein the one or more RDLs electrically couple to the third IC die and the TIVs.

### Claim 22 (depends on 21)

The image sensor package according to claim 21, wherein at least one of the TSVs extends from the bottom of the second IC die to a top of the second IC die.

### Claim 23 (depends on 21)

The image sensor package according to claim 21, wherein the second IC die comprises an interconnect structure over the semiconductor substrate, and wherein the TSVs terminates at a bottom of the interconnect structure.

### Claim 24 (depends on 23)

The image sensor package according to claim 23, wherein the interconnect structure comprises an interlayer dielectric (ILD) layer and a plurality of second interconnect layers stacked in the ILD layer.

### Claim 25 (depends on 24)

The image sensor package according to claim 24, wherein the TSVs extend completely through the semiconductor substrate and the interconnect structure, wherein the second IC die comprises a pair of second TSVs between which the TSVs are laterally spaced, and wherein the second TSVs extend through the semiconductor substrate, from the bottom of the second IC die, to contact with a second interconnect layer of the interconnect structure.

### Claim 26 (depends on 25)

The image sensor package according to claim 25, wherein the fan-out structure further comprises a pair of second TIVs extending through the fan-out dielectric layer, such that the TIVs and the third IC die are laterally spaced between the second TIVs, and wherein the second TIVs are aligned with and electrically coupled to the second TSVs, respectively.

### Claim 27 (depends on 21)

The image sensor package according to claim 21, wherein opposite sidewalls of the fan-out structure are respectively aligned to opposite sidewalls of the second IC die, and are respectively aligned to opposite sidewalls of the first IC die.

### Claim 28 (depends on 21)

The image sensor package according to claim 21, wherein third IC die comprises a bond pad on an underside of the third IC die, wherein a bottom surface of the bond pad is even with a bottom surface of the fan-out dielectric layer, and wherein the one or more RDLs comprise a conductive line extending continuously from contact with the bottom surface of the bond pad to contact with a bottom surface of one of the TIVs.

### Claim 29 (depends on 21)

The image sensor package according to claim 21, wherein the fan-out structure comprises a fourth IC die arranged laterally adjacent to the third IC die, such that the third and fourth IC dies are laterally spaced between the TIVs.

### Claim 30 (depends on 1)

The image sensor package according to claim 1, wherein the second IC die comprises a semiconductor substrate and an interconnect structure, wherein the semiconductor substrate and the interconnect structure are vertically stacked, and wherein the interconnect structure comprises an alternating stack of conductive lines and conductive vias.

### Claim 31 (depends on 2)

The image sensor package according to claim 2, wherein the first IC die further comprises an additional semiconductor substrate and a first interconnect structure under the additional semiconductor substrate, wherein the pixel sensor array is between the additional semiconductor substrate and the first interconnect structure, and wherein the second IC die further comprises a second interconnect structure over the semiconductor substrate.