# US 2018/0026039 A1 · Semiconductor device and manufacture method thereof

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- Number: US 2018/0026039 A1
- Document ID: US20180026039A1
- Status: Published application
- Kind: A1
- Application number: 15/722,229
- Filed: 2017-10-02
- Published: 2018-01-25
- Earliest claimed: 2016-02-19
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Limited
- Inventors: Che-Cheng CHANG; Chih-Han LIN; Horng-Huei TSENG
- Web page: https://patentgrep.com/patent/US20180026039A1

## CPC

- H10D 84/853: {comprising FinFETs}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/666: {the conductor further comprising additional layers}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/8316: {the IGFETs characterised by having gate sidewall spacers specially adapted for integration}
- H10D 84/834: {comprising FinFETs}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a semiconductor substrate and at least one gate stack. The gate stack is present on the semiconductor substrate, and the gate stack includes at least one work function conductor and a filling conductor. The work function conductor has a recess therein. The filling conductor includes a plug portion and a cap portion. The plug portion is present in the recess of the work function conductor. The cap portion caps the work function conductor.

## Claims

### Claim 1

A semiconductor device, comprising:
a first gate stack comprising:
a first work function conductor; and
a first filling conductor comprising a plug portion and a cap portion, wherein:
the plug portion of the first filling conductor is disposed between a first sidewall of the first work function conductor and a second sidewall of the first work function conductor, and
the cap portion of the first filling conductor overlies an uppermost surface of the first work function conductor; and
a first gate spacer disposed on a first side of the first gate stack and a second gate spacer disposed on a second side of the first gate stack opposite the first side, wherein:
a sidewall of the cap portion and the first sidewall of the first work function conductor are in direct contact with a sidewall of the first gate spacer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, the first gate stack comprising a second work function conductor disposed between the plug portion of the first filling conductor and the first sidewall of the first work function conductor and between the plug portion of the first filling conductor and the second sidewall of the first work function conductor.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the first work function conductor is a p-type work function conductor and the second work function conductor is an n-type work function conductor.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, comprising a dielectric cap, wherein the dielectric cap is separated from the first work function conductor by the cap portion of the first filling conductor.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, comprising:
a second gate stack comprising:
the first work function conductor;
a second work function conductor; and
a second filling conductor comprising a plug portion and a cap portion, wherein:
the plug portion of the second filling conductor is disposed between a first sidewall of the second work function conductor and a second sidewall of the second work function conductor,
the plug portion of the second filling conductor is separated from the first work function conductor by the second work function conductor, and
the cap portion of the second filling conductor overlies an uppermost surface of the first work function conductor and an uppermost surface of the second work function conductor.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the first gate stack is a p-type gate stack and the second gate stack is an n-type gate stack.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, comprising a semiconductor fin disposed below the first gate stack.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, comprising:
a second gate stack comprising the first work function conductor, wherein:
a portion of the first work function conductor of the first gate stack has a first tapered profile, and
a portion of the first work function conductor of the second gate stack has a second tapered profile different than the first tapered profile.

### Claim 9

A semiconductor device, comprising:
a first gate spacer and a second gate spacer; and
a gate stack disposed between the first gate spacer and the second gate spacer, the gate stack comprising:
a gate dielectric in direct contact with the first gate spacer and the second gate spacer;
a first work function conductor over the gate dielectric and in direct contact with the first gate spacer and the second gate spacer; and
a filling conductor comprising a plug portion and a cap portion, wherein:
the plug portion is disposed between a first sidewall of the first work function conductor and a second sidewall of the first work function conductor, and
the cap portion caps the first work function conductor.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the first work function conductor is in direct contact with a top surface of the gate dielectric.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein the cap portion of the filling conductor is in direct contact with the first gate spacer and the second gate spacer.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, comprising:
a dielectric cap, wherein the dielectric cap is separated from the first work function conductor by the cap portion of the filling conductor.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, comprising a second work function conductor disposed between the first work function conductor and the plug portion of the filling conductor.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the first work function conductor is disposed between the second work function conductor and the gate dielectric.

### Claim 15

A method of manufacturing a semiconductor device, the method comprising:
forming a first gate spacer and a second gate spacer;
forming a first work function conductor between the first gate spacer and the second gate spacer, wherein the first work function conductor defines a recess;
forming a mask in a portion of the recess to conceal a first portion of the first work function conductor, wherein a second portion of the first work function conductor is not concealed by the mask;
recessing the first work function conductor between the first gate spacer and the second gate spacer to expose a first portion of a sidewall of the first gate spacer and a first portion of a sidewall of the second gate spacer;
removing the mask after the recessing the first work function conductor;
forming a filling conductor in the recess and in a space between the first portion of the sidewall of the first gate spacer and the first portion of the sidewall of the second gate spacer; and
recessing the filling conductor to expose a second portion of the sidewall of the first gate spacer and a second portion of the sidewall of the second gate spacer.

### Claim 16 (depends on 15)

The method of claim 15, wherein the recessing the first work function conductor comprises tapering some of the second portion of the first work function conductor.

### Claim 17 (depends on 15)

The method of claim 15, comprising:
forming a dielectric cap between the second portion of the sidewall of the first gate spacer and the second portion of the sidewall of the second gate spacer.

### Claim 18 (depends on 15)

The method of claim 15, comprising:
forming a second work function conductor between the first gate spacer and the second gate spacer before the forming a first work function conductor.

### Claim 19 (depends on 18)

The method of claim 18, comprising recessing the second work function conductor, wherein the recessing the second work function conductor comprises tapering some of the second work function conductor.

### Claim 20 (depends on 18)

The method of claim 18, wherein the first work function conductor is an n-type work function conductor and the second work function conductor is a p-type work function conductor.