# US 2018/0026034 A1 · Semiconductor structure with low defect

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- Number: US 2018/0026034 A1
- Document ID: US20180026034A1
- Status: Published application
- Kind: A1
- Application number: 15/720,366
- Filed: 2017-09-29
- Published: 2018-01-25
- Earliest claimed: 2016-03-07
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Blandine DURIEZ; Georgios VELLIANITIS
- Web page: https://patentgrep.com/patent/US20180026034A1

## CPC

- H10D 84/834: {comprising FinFETs}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10P 50/283: {by chemical means}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor structures are provided. The semiconductor structure includes a fin structure formed over a substrate and an isolation structure formed around the fin structure. The semiconductor structure further includes a nanowire structure formed over the fin structure and a gate structure formed around the nanowire structure. In addition, a bottommost of the nanowire structure is lower than a top surface of the isolation structure.

## Claims

### Claim 1

A semiconductor structure, comprising:
a fin structure formed over a substrate;
an isolation structure formed around the fin structure;
a nanowire structure formed over the fin structure; and
a gate structure formed around the nanowire structure, wherein a bottommost of the nanowire structure is lower than a top surface of the isolation structure.

### Claim 2 (depends on 1)

The semiconductor structure as claimed in claim 1, wherein the nanowire structure and the fin structure are separated by a cavity.

### Claim 3 (depends on 1)

The semiconductor structure as claimed in claim 1, wherein the gate structure and the fin structure are separated by a cavity.

### Claim 4 (depends on 1)

The semiconductor structure as claimed in claim 1, further comprising:
a source/drain structure formed in the nanowire structure, wherein a cavity is located under the source/drain structure.

### Claim 5 (depends on 4)

The semiconductor structure as claimed in claim 4, wherein a bottom surface of the source/drain structure is exposed by the cavity.

### Claim 6 (depends on 4)

The semiconductor structure as claimed in claim 4, wherein the cavity extends under the gate structure.

### Claim 7 (depends on 1)

The semiconductor structure as claimed in claim 1, wherein the nanowire structure has a wider top portion and a narrower bottom portion.

### Claim 8

A semiconductor structure, comprising:
a fin structure formed over a substrate;
an isolation structure formed around the fin structure;
a nanowire structure formed over the fin structure;
a gate structure formed around the nanowire structure; and
a source/drain structure formed in the nanowire structure adjacent to the gate structure, wherein a cavity is located under the source/drain structure.

### Claim 9 (depends on 8)

The semiconductor structure as claimed in claim 8, wherein the cavity extends under the gate structure.

### Claim 10 (depends on 8)

The semiconductor structure as claimed in claim 8, wherein a bottommost of the nanowire structure is lower than a top surface of the isolation structure.

### Claim 11 (depends on 8)

The semiconductor structure as claimed in claim 8, wherein a bottommost of the gate structure is lower than a top surface of the isolation structure.

### Claim 12 (depends on 8)

The semiconductor structure as claimed in claim 8, wherein a height of the cavity under the source/drain structure is in a range from about 50 nm to about 300 nm.

### Claim 13 (depends on 8)

The semiconductor structure as claimed in claim 8, wherein the nanowire structure has a wider top portion and a narrower bottom portion.

### Claim 14

A semiconductor structure, comprising:
a fin structure formed over a substrate;
an isolation structure formed around the fin structure;
a nanowire structure formed over the fin structure;
a gate structure formed around the nanowire structure;
a spacer formed on a sidewall of the gate structure; and
a source/drain structure formed in the nanowire structure adjacent to the gate structure,
wherein the source/drain structure and the fin structure are separated by a cavity.

### Claim 15 (depends on 14)

The semiconductor structure as claimed in claim 14, wherein a bottommost of the source/drain structure is lower than a top surface of the isolation structure.

### Claim 16 (depends on 14)

The semiconductor structure as claimed in claim 14, wherein the gate structure extends directly below the spacer.

### Claim 17 (depends on 14)

The semiconductor structure as claimed in claim 14, wherein the nanowire structure has a wider top portion and a narrower bottom portion.

### Claim 18 (depends on 14)

The semiconductor structure as claimed in claim 14, wherein a width of the nanowire structure is greater than a width of the fin structure.

### Claim 19 (depends on 14)

The semiconductor structure as claimed in claim 14, wherein a width of a top surface of the nanowire structure is greater than a width of a bottom surface of the nanowire structure, and the width of the bottom surface of the nanowire structure is greater than a width of a top surface of the fin structure.

### Claim 20 (depends on 19)

The semiconductor structure as claimed in claim 19, wherein the width of the bottom surface of the nanowire structure is substantially equal to a width of the cavity under the source/drain structure.