# US 2018/0026023 A1 · Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP

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- Number: US 2018/0026023 A1
- Document ID: US20180026023A1
- Status: Published application
- Kind: A1
- Application number: 15/676,488
- Filed: 2017-08-14
- Published: 2018-01-25
- Earliest claimed: 2008-12-12
- Assignees: STATS ChipPAC Pte. Ltd.
- Applicants: STATS ChipPAC Pte. Ltd.
- Inventors: Yaojian Lin; Kang Chen; Seung Wook Yoon
- Web page: https://patentgrep.com/patent/US20180026023A1

## CPC

- H10W 90/00: Package configurations
- H10P 72/74: {using temporarily an auxiliary support}
- H10P 72/7402: {Wafer tapes, e.g. grinding or dicing support tapes}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/42: Vias, e.g. via plugs
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 42/276: {the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/635: {Through-vias}
- H10W 74/01: Manufacture or treatment
- H10W 74/014: {using batch processing}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10W 46/301: {for alignment}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/01223: {in liquid form, e.g. by dispensing droplets or by screen printing}
- H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/019: {of bond pads}
- H10W 72/01904: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/0198: {batch processes}
- H10W 72/07131: {Means for applying material, e.g. for deposition or forming coatings}
- H10W 72/072: {of bump connectors}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/232: {Plan-view shape, i.e. in top view}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/874: {On different surfaces}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/9413: {on encapsulations}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/10: characterised by their shape or disposition
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure.

## Claims

### Claim 1

A method of making a semiconductor device, comprising:
providing a semiconductor die;
depositing an encapsulant over semiconductor die;
forming an insulating layer over the encapsulant and semiconductor die;
forming a plurality of first openings through the insulating layer; and
forming a conductive layer over the plurality of first openings.

### Claim 2 (depends on 1)

The method of claim 1, further including forming the conductive layer continuously over each of the first openings to form a micro conductive via array.

### Claim 3 (depends on 2)

The method of claim 2, further including forming a trench in the insulating layer surrounding the micro conductive via array, wherein the conductive layer extends into the trench.

### Claim 4 (depends on 3)

The method of claim 3, further including forming the conductive layer completely filling the trench.

### Claim 5 (depends on 1)

The method of claim 1, further including:
forming a second opening in the encapsulant over the first openings of the insulating layer; and
forming a conductive bump in the second opening on the conductive layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein the semiconductor die includes a sensor.

### Claim 7

A method of making a semiconductor device, comprising:
providing a semiconductor die;
forming an insulating layer over the semiconductor die;
forming a plurality of first openings through the insulating layer; and
forming a conductive layer over the plurality of first openings.

### Claim 8 (depends on 7)

The method of claim 7, further including forming the conductive layer continuously over each of the first openings to form a micro conductive via array.

### Claim 9 (depends on 7)

The method of claim 7, further including forming a trench around the first openings.

### Claim 10 (depends on 9)

The method of claim 9, further including forming the conductive layer into the plurality of first openings and the trench.

### Claim 11 (depends on 7)

The method of claim 7, further including:
depositing an encapsulant over the semiconductor die; and
forming the plurality of first openings through the insulating layer over the encapsulant.

### Claim 12 (depends on 11)

The method of claim 11, further including forming a second opening in the encapsulant over the first openings of the insulating layer.

### Claim 13 (depends on 12)

The method of claim 12, further including forming a bump in the second opening.

### Claim 14

A semiconductor device, comprising:
a semiconductor die;
an encapsulant deposited around the semiconductor die including an opening formed through the encapsulant; and
a conductive layer formed over the encapsulant including a plurality of conductive vias formed within a footprint of the opening.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, further including a conductive bump formed in the opening and contacting each of the plurality of conductive vias.

### Claim 16 (depends on 14)

The semiconductor device of claim 14, further including an insulating layer formed between the encapsulant and conductive layer, wherein the opening extends to the conductive layer through the insulating layer.

### Claim 17 (depends on 14)

The semiconductor device of claim 14, wherein the conductive layer further includes a conductive ring around the plurality of conductive vias.

### Claim 18 (depends on 14)

The semiconductor device of claim 14, wherein the conductive layer extends from the plurality of conductive vias to a contact pad of the semiconductor die.

### Claim 19 (depends on 14)

The semiconductor device of claim 14, further including an insulating layer formed over the encapsulant opposite the conductive layer, wherein the opening extends through the insulating layer.

### Claim 20 (depends on 14)

The semiconductor device of claim 14, wherein the semiconductor die includes a sensor.

### Claim 21

A semiconductor device, comprising:
a semiconductor die; and
a conductive layer formed over the semiconductor die and including a micro conductive via array.

### Claim 22 (depends on 21)

The semiconductor device of claim 21, further including a conductive bump formed over the micro conductive via array.

### Claim 23 (depends on 21)

The semiconductor device of claim 21, further including an insulating layer formed between the semiconductor die and conductive layer.

### Claim 24 (depends on 21)

The semiconductor device of claim 21, further including an encapsulant deposited over the semiconductor die.

### Claim 25 (depends on 24)

The semiconductor device of claim 24, further including an opening in the encapsulant over the micro conductive via array.