# US 2018/0026019 A1 · Package-on-Package Devices with WLP Components with Dual RDLS for Surface Mount Dies and Methods Therefor

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- Number: US 2018/0026019 A1
- Document ID: US20180026019A1
- Status: Published application
- Kind: A1
- Application number: 15/393,112
- Filed: 2016-12-28
- Published: 2018-01-25
- Earliest claimed: 2016-07-22
- Assignees: Invensas Corporation
- Applicants: Invensas Corporation
- Inventors: Min Tao; Hoki Kim; Ashok S. Prabhu; Zhuowen Sun; Wael Zohni; Belgacem Haba
- Web page: https://patentgrep.com/patent/US20180026019A1

## CPC

- H10W 90/00: Package configurations
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/095: {of vias therein}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 72/071: {Connecting or disconnecting}
- H10W 72/073: {of die-attach connectors}
- H10W 72/50: Bond wires
- H10W 72/90: Bond pads, in general
- H10W 74/016: {using moulds}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/63: Vias, e.g. via plugs
- H10W 70/655: Fan-out layouts
- H10W 70/681: {comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/20: Configurations of stacked chips
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Package-on-package (“PoP”) devices with WLP (“WLP”) components with dual RDLs (“RDLs”) for surface mount dies and methods therefor. In a PoP, a first IC die surface mount coupled to an upper surface of a package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region. A molding layer is formed over the upper surface of the package substrate. A first and a second WLP microelectronic component are located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines. Each of the first and the second WLP microelectronic components have a second IC die located between a first RDL and a second RDL. A third and a fourth IC die are respectively surface mount coupled over the first and the second WLP microelectronic components.

## Claims

### Claim 1

A package-on-package device, comprising:
a package substrate;
a first integrated circuit die surface mount coupled to an upper surface of the package substrate;
conductive lines coupled to the upper surface of the package substrate in a fan-out region, the first conductive lines extending away from the upper surface of the package substrate;
a molding layer formed over the upper surface of the package substrate, around sidewall surfaces of the first integrated circuit die, and around bases and shafts of the conductive lines;
a first and a second wafer-level packaged microelectronic component located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines;
each of the first and the second wafer-level packaged microelectronic components having a second integrated circuit die located between a first redistribution layer and a second redistribution layer; and
a third and a fourth integrated circuit die respectively surface mount coupled over the first and the second wafer-level packaged microelectronic components.

### Claim 2 (depends on 1)

The package-on-package device according to claim 1, wherein each of the first and the second wafer-level packaged microelectronic components comprises:
the second integrated circuit die having first contacts in an inner third region of a first surface of the second integrated circuit die;
the first redistribution layer having second contacts in an inner third region of a first surface of the first redistribution layer and third contacts in an outer third region of a second surface of the first redistribution layer opposite the first surface thereof;
the second contacts of the first redistribution layer coupled for electrical conductivity to the first contacts of the second integrated circuit die with the first surface of the second integrated circuit die face-to-face with the first surface of the first redistribution layer; and
the third contacts offset from the second contacts for being positioned in a fan-out region for association at least with the outer third region of the second surface of the first redistribution layer, the third contacts being surface mount contacts.

### Claim 3 (depends on 2)

The package-on-package device according to claim 2, wherein each of the first and the second wafer-level packaged microelectronic components comprises:
the second redistribution layer having fourth contacts in an inner third region of a first surface of the second redistribution layer and interconnects in an outer third region of a second surface of the second redistribution layer opposite the first surface thereof;
the second integrated circuit die having through die vias in an outer third region of the first surface and a second surface opposite the first surface;
the interconnects of the second redistribution layer coupled for electrical conductivity to the through die vias of the second integrated circuit die with the second surface of the second integrated circuit die face-to-face with the second surface of the second redistribution layer; and
the interconnects offset from the fourth contacts for being positioned in the fan-out region for association at least with the outer third region of the second surface of each of the first redistribution layer and the second redistribution layer.

### Claim 4 (depends on 3)

The package-on-package device according to claim 3, wherein each of the third and the fourth integrated circuit dies comprises fifth contacts in an inner third region of respective surfaces of the third and the fourth integrated circuit dies.

### Claim 5 (depends on 4)

The package-on-package device according to claim 4, wherein the fourth contacts of the second redistribution layer for each of the first and the second wafer-level packaged microelectronic components are coupled for electrical conductivity respectively to the fifth contacts of the third and the fourth integrated circuit dies, respectively, with the respective surfaces of the third and the fourth integrated circuit dies face-to-face with the first surface of the second redistribution layer of the first and the second wafer-level packaged microelectronic components, respectively.

### Claim 6 (depends on 1)

The package-on-package device according to claim 1, wherein the conductive lines are wire bond wires.

### Claim 7 (depends on 1)

The package-on-package device according to claim 1, wherein the package substrate includes a fan-out wafer-level redistribution layer.

### Claim 8 (depends on 4)

The package-on-package device according to claim 4, wherein:
the first integrated circuit die is a controller die;
each of the first and the second wafer-level packaged microelectronic component comprises a respective first memory die; and
the second and the third integrated circuit die are respective second memory dies.

### Claim 9 (depends on 1)

The package-on-package device according to claim 1, wherein the conductive lines are conductive pillars.

### Claim 10 (depends on 1)

The package-on-package device according to claim 1, wherein the conductive lines are conductive vias.

### Claim 11

A method for forming a package-on-package device, comprising:
obtaining a package substrate;
first surface mount coupling a first integrated circuit die to an upper surface of the package substrate;
coupling conductive lines to the upper surface of the package substrate in a fan-out region, the first conductive lines extending away from the upper surface of the package substrate;
forming a molding layer over the upper surface of the package substrate, around sidewall surfaces of the first integrated circuit die, and around bases and shafts of the conductive lines;
second surface mount coupling a first and a second wafer-level packaged microelectronic component located at a same level above an upper surface of the molding layer respectively to sets of upper portions of the conductive lines;
each of the first and the second wafer-level packaged microelectronic components having a second integrated circuit die located between a first redistribution layer and a second redistribution layer; and
third surface mount coupling a third and a fourth integrated circuit die respectively over the first and the second wafer-level packaged microelectronic components.

### Claim 12 (depends on 11)

The method according to claim 11, wherein each of the first and the second wafer-level packaged microelectronic components comprises:
the second integrated circuit die having first contacts in an inner third region of a first surface of the second integrated circuit die;
the first redistribution layer having second contacts in an inner third region of a first surface of the first redistribution layer and third contacts in an outer third region of a second surface of the first redistribution layer opposite the first surface thereof;
the second contacts of the first redistribution layer coupled for electrical conductivity to the first contacts of the second integrated circuit die with the first surface of the second integrated circuit die face-to-face with the first surface of the first redistribution layer; and
the third contacts offset from the second contacts for being positioned in a fan-out region for association at least with the outer third region of the second surface of the first redistribution layer, the third contacts being surface mount contacts.

### Claim 13 (depends on 12)

The method according to claim 12, wherein each of the first and the second wafer-level packaged microelectronic components comprises:
the second redistribution layer having fourth contacts in an inner third region of a first surface of the second redistribution layer and interconnects in an outer third region of a second surface of the second redistribution layer opposite the first surface thereof;
the second integrated circuit die having through die vias in an outer third region of the first surface and a second surface opposite the first surface;
the interconnects of the second redistribution layer coupled for electrical conductivity to the through die vias of the second integrated circuit die with the second surface of the second integrated circuit die face-to-face with the second surface of the second redistribution layer; and
the interconnects offset from the fourth contacts for being positioned in the fan-out region for association at least with the outer third region of the second surface of each of the first redistribution layer and the second redistribution layer.

### Claim 14 (depends on 13)

The method according to claim 13, wherein each of the third and the fourth integrated circuit dies comprises fifth contacts in an inner third region of respective surfaces of the third and the fourth integrated circuit dies.

### Claim 15 (depends on 14)

The method according to claim 14, wherein the third surface mount coupling comprises:
coupling the fourth contacts of the second redistribution layer for each of the first and the second wafer-level packaged microelectronic components for electrical conductivity respectively to the fifth contacts of the third and the fourth integrated circuit dies, respectively, with the respective surfaces of the third and the fourth integrated circuit dies face-to-face with the first surface of the second redistribution layer of the first and the second wafer-level packaged microelectronic components, respectively.

### Claim 16 (depends on 11)

The method according to claim 11, wherein the conductive lines are wire bond wires.

### Claim 17 (depends on 11)

The method according to claim 11, wherein the package substrate includes a fan-out wafer-level redistribution layer.

### Claim 18 (depends on 11)

The method according to claim 11, wherein:
the first integrated circuit die is a controller die;
each of the first and the second wafer-level packaged microelectronic component comprises a respective first memory die for the second integrated circuit die respectively thereof; and
the second and the third integrated circuit die are respective second memory dies.

### Claim 19 (depends on 11)

The method according to claim 11, wherein the conductive lines are conductive pillars.

### Claim 20 (depends on 11)

The method according to claim 11, wherein the conductive lines are conductive vias.