# US 2018/0026017 A1 · Dies-on-Package Devices and Methods Therefor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0026017 A1 - Document ID: US20180026017A1 - Status: Published application - Kind: A1 - Application number: 15/393,068 - Filed: 2016-12-28 - Published: 2018-01-25 - Earliest claimed: 2016-07-22 - Assignees: Invensas Corporation - Applicants: Invensas Corporation - Inventors: Min Tao; Hoki Kim; Ashok S. Prabhu; Zhuowen Sun; Wael Zohni; Belgacem Haba - Web page: https://patentgrep.com/patent/US20180026017A1 ## CPC - H10W 90/00: Package configurations - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/095: {of vias therein} - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/611: {for connecting multiple chips together} - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/635: {Through-vias} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/685: comprising multiple insulating layers - H10W 72/071: {Connecting or disconnecting} - H10W 72/073: {of die-attach connectors} - H10W 72/50: Bond wires - H10W 72/90: Bond pads, in general - H10W 74/016: {using moulds} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation} - H10W 74/129: {forming a chip-scale package [CSP]} - H10W 74/131: {the semiconductor body being only partially enclosed} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/63: Vias, e.g. via plugs - H10W 70/655: Fan-out layouts - H10W 70/681: {comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/59: Bond pads specially adapted therefor - H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip} - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 90/20: Configurations of stacked chips - H10W 90/288: {characterised by arrangements for thermal management of the stacked chips} - H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips} - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/752: {between stacked chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Dies-on-package devices and methods therefor are disclosed. In a dies-on-package device, a first IC die is surface mount coupled to an upper surface of a package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region with respect to the first IC die. A molding layer is formed over the upper surface of the package substrate, around sidewall surfaces of the first IC die, and around bases and shafts of the conductive lines. A plurality of second IC dies is located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines. The plurality of second IC dies are respectively coupled to the sets of the conductive lines in middle third portions respectively of the plurality of second IC dies for corresponding fan-in regions thereof. ## Claims ### Claim 1 A dies-on-package device, comprising: a package substrate; a first integrated circuit die surface mount coupled to an upper surface of the package substrate; conductive lines coupled to the upper surface of the package substrate in a fan-out region with respect to the first integrated circuit die, the first conductive lines extending away from the upper surface of the package substrate; a molding layer formed over the upper surface of the package substrate, around sidewall surfaces of the first integrated circuit die, and around bases and shafts of the conductive lines; and a plurality of second integrated circuit dies located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines; the plurality of second integrated circuit dies respectively coupled to the sets of the conductive lines in middle third portions respectively of the plurality of second integrated circuit dies for corresponding fan-in regions thereof. ### Claim 2 (depends on 1) The dies-on-package device according to claim 1, wherein the conductive lines are wire bond wires. ### Claim 3 (depends on 1) The dies-on-package device according to claim 1, wherein the package substrate is a laminate substrate having at least two layers. ### Claim 4 (depends on 1) The dies-on-package device according to claim 1, wherein the package substrate includes a fan-out wafer-level redistribution layer. ### Claim 5 (depends on 4) The dies-on-package device according to claim 4, wherein: the first integrated circuit die is a controller die; and each of the wafer-level packaged microelectronic components comprises a respective memory die. ### Claim 6 (depends on 1) The dies-on-package device according to claim 1, wherein the conductive lines are conductive pillars. ### Claim 7 (depends on 1) The dies-on-package device according to claim 1, wherein the conductive lines are conductive vias. ### Claim 8 (depends on 1) The dies-on-package device according to claim 1, wherein an overall package height of the dies-on-package device is in a range of approximately ______ to ______ millimeters. ### Claim 9 (depends on 1) The dies-on-package device according to claim 1, wherein: the plurality of second integrated circuit dies are laid out to form a quadrangle-like shape defining an area in a center thereof; contacts of the plurality of second integrated circuit dies located in the middle third region are in rows; and the rows of nearest neighbors of the plurality of second integrated circuit dies are orthogonal to one another. ### Claim 10 (depends on 1) The dies-on-package device according to claim 1, wherein: the plurality of second integrated circuit dies are laid out to form a quadrilateral-like shape; contacts of the plurality of second integrated circuit dies located in the middle third region are in rows; the rows of a first two of the plurality of second integrated circuit dies are parallel with one another to form first extended rows; the rows of a second two of the plurality of second integrated circuit dies are parallel with one another to form second extended rows; and the first extended rows and the second extended rows are opposite and parallel with one another. ### Claim 11 (depends on 1) The dies-on-package device according to claim 1, wherein surface area portions of each of the plurality of second integrated circuit dies overlap the first integrated circuit die. ### Claim 12 (depends on 1) The dies-on-package device according to claim 1, wherein the plurality of second integrated circuit dies is a first plurality of second integrated circuit dies, wherein the sets of upper portions of the conductive lines are first sets of upper portions of the conductive lines, the dies-on-package device further comprising: a second plurality of second integrated circuit dies located at a same level above upper surfaces of the first plurality of integrated circuit dies respectively surface mount coupled to second sets of upper portions of the conductive lines; and the second plurality of second integrated circuit dies respectively coupled to the second sets of the conductive lines in middle third portions respectively of the second plurality of second integrated circuit dies for corresponding fan-in regions thereof. ### Claim 13 (depends on 12) The dies-on-package device according to claim 12, wherein the conductive lines are wire bond wires. ### Claim 14 (depends on 12) The dies-on-package device according to claim 12, wherein surface area portions of each of the first plurality of second integrated circuit dies and the second plurality of second integrated circuit dies overlap the first integrated circuit die. ### Claim 15 (depends on 12) The dies-on-package device according to claim 12, wherein surface area portions of each of the second plurality of second integrated circuit dies overlap the first integrated circuit die and the first plurality of second integrated circuit dies. ### Claim 16 A method for forming a dies-on-package device, comprising: obtaining a package substrate; first surface mount interconnecting a first integrated circuit die to an upper surface of the package substrate; coupling conductive lines to the upper surface of the package substrate in a fan-out region, the conductive lines extending away from the upper surface of the package substrate; forming a molding layer over the upper surface of the package substrate, around sidewall surfaces of the first integrated circuit die, and around bases and shafts of the conductive lines; and second surface mount interconnecting a plurality of second integrated circuit dies above an upper surface of the first molding layer, the second surface mount interconnecting including coupling sets of upper portions of the conductive lines respectively to the plurality of second integrated circuit dies for corresponding fan-in regions thereof. ### Claim 17 (depends on 16) The method according to claim 16, wherein surface area portions of each of the plurality of second integrated circuit dies overlap the first integrated circuit die. ### Claim 18 (depends on 16) The method according to claim 16, wherein the plurality of second integrated circuit dies is a first plurality of second integrated circuit dies, wherein the sets of upper portions of the conductive lines are first sets of upper portions of the conductive lines, the method further comprising: third surface mount interconnecting a second plurality of second integrated circuit dies located at a same level above upper surfaces of the first plurality of integrated circuit dies to second sets of upper portions of the conductive lines; and the second plurality of second integrated circuit dies respectively coupled to the second sets of the conductive lines in middle third portions respectively of the second plurality of second integrated circuit dies for corresponding fan-in regions thereof. ### Claim 19 (depends on 18) The method according to claim 18, wherein surface area portions of each of the second plurality of second integrated circuit dies overlap the first integrated circuit die and the first plurality of second integrated circuit dies.