# US 2018/0026014 A1 · Package-on-Package Structure with Through Molding Via > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0026014 A1 - Document ID: US20180026014A1 - Status: Published application - Kind: A1 - Application number: 15/722,758 - Filed: 2017-10-02 - Published: 2018-01-25 - Earliest claimed: 2013-09-12 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Ming-Chih Yew; Fu-Jen Li; Po-Yao Lin; Kuo-Chuan Liu - Web page: https://patentgrep.com/patent/US20180026014A1 ## CPC - H10W 90/00: Package configurations - H05K 1/0271: {Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion} - H05K 1/11: Printed elements for providing electric connections to or between printed circuits - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10W 70/095: {of vias therein} - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/635: {Through-vias} - H10W 70/65: Shapes or dispositions of interconnections - H10W 74/016: {using moulds} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/131: {the semiconductor body being only partially enclosed} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H05K 2201/09063: Holes or slots in insulating substrate not used for electrical connections - H05K 2201/10378: Interposers - H05K 2201/10613: Details of electrical connections of non-printed components, e.g. special leads - H05K 2201/10734: Ball grid array [BGA]; Bump grid array - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip} - H10W 74/10: characterised by their shape or disposition - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 90/20: Configurations of stacked chips - H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/732: {between stacked chips} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ## Abstract Disclosed herein is a device comprising a first package having a first side with a plurality of connectors disposed thereon and a second package mounted on the first package by the connectors. A molding compound is disposed on the first side of the first package and between the first package and the second package. A plurality of stress relief structures (SRSs) are disposed in the molding compound, the plurality of SRSs each comprising a cavity free of metal in the molding compound and spaced apart from each of the plurality of connectors. ## Claims ### Claim 1 A device package comprising: a semiconductor die disposed on a surface of a package substrate; a first conductive connector and a second conductive connector both disposed on the surface of the package substrate; a molding compound encapsulating the semiconductor die, a first sidewall of the molding compound circumferentially surrounding the first conductive connector and a second sidewall of the molding compound circumferentially surrounding the second conductive connector, the first sidewall being disposed outside of a region surrounded by the second sidewall, the second sidewall being disposed outside of a region surrounded by the first sidewall; a cavity extending through the molding compound, wherein no conductive connectors are disposed in the cavity, and wherein an entirety of the cavity is disposed between the first sidewall of the molding compound and the second sidewall of the molding compound in a top-down view of the device package. ### Claim 2 (depends on 1) The device package of claim 1, wherein the first conductive connector and the second conductive connector bonds the package substrate to a second package substrate. ### Claim 3 (depends on 2) The device package of claim 2, wherein semiconductor die is disposed between the second package substrate and the package substrate. ### Claim 4 (depends on 2) The device package of claim 2 further comprising a plurality of stacked dies bonded to a surface of the second package substrate opposite the first conductive connector. ### Claim 5 (depends on 1) The device package of claim 1, wherein the first conductive connector comprises a solder region. ### Claim 6 (depends on 5) The device package of claim 5, wherein the solder region is in physical contact with the first sidewall of the molding compound. ### Claim 7 (depends on 1) The device package of claim 1, wherein the semiconductor die is clip chip bonded to the surface of the package substrate by a plurality of third conductive connectors, wherein a size of the plurality of third conductive connectors is different from a size of the first conductive connector. ### Claim 8 A device package comprising: a semiconductor die flip-chip bonded to first contact pads at a surface of a first substrate; a second substrate flip-chip bonded to second contact pads at the surface of the first substrate by a plurality of connectors; a molding compound encapsulating the semiconductor die, the molding compound comprising a plurality of sidewalls, the plurality of sidewalls encircling each of the plurality of connectors in a top-down view, and a portion of the molding compound is disposed between each of the plurality of connectors; a cavity extending through the molding compound, the cavity being free of any conductive features disposed therein, wherein a top and bottom of each of the plurality of connectors are disposed at a same level with a respective top and bottom of the cavity, and wherein the cavity has a same shape in a plan view as each of the plurality of sidewalls. ### Claim 9 (depends on 8) The device package of claim 8, wherein the cavity comprises air. ### Claim 10 (depends on 8) The device package of claim 8, wherein a total surface area of all cavities within the molding compound is 1% to 15% of a total surface area of the molding compound. ### Claim 11 (depends on 8) The device package of claim 8, wherein an area of a region bounded by a first one of the plurality of sidewalls is greater than an area of the cavity in a top down view. ### Claim 12 (depends on 8) The device package of claim 8, wherein the semiconductor die is flip-chip bonded to the first contact pads by a second plurality of connectors, a pitch of the second plurality of connectors being smaller than a pitch of the plurality of connectors. ### Claim 13 (depends on 8) The device package of claim 8, wherein the cavity is disposed between a first one of the plurality of sidewalls and a second one of the plurality of sidewalls. ### Claim 14 (depends on 8) The device package of claim 8, further comprising a second cavity extending through the molding compound, the second cavity being physically separated from the cavity, and wherein both the cavity and the second cavity are disposed between a first one of the plurality of sidewalls and a second one of the plurality of sidewalls. ### Claim 15 A device comprising: a first package having a first side with a plurality of connectors disposed thereon; a second package bonded to the first package by the plurality of connectors; a molding compound disposed between the first side of the first package and the second package, a continuous sidewall of the molding compound completely encircles at least two of the plurality of connectors, and wherein no molding compound is disposed between any of the at least two of the plurality of connectors; and a cavity extending through the molding compound, wherein the cavity is free of metal disposed therein. ### Claim 16 (depends on 15) The device of claim 15 further comprising a semiconductor die bonded to the first side of the first package. ### Claim 17 (depends on 16) The device of claim 16, wherein the molding compound encapsulates the semiconductor die. ### Claim 18 (depends on 16) The device of claim 16, wherein the semiconductor die is disposed between the first package and the second package ### Claim 19 (depends on 15) The device of claim 15, wherein a height of the cavity is equal to a height of the continuous sidewall of the molding compound. ### Claim 20 (depends on 15) The device of claim 15 further comprising a plurality of second connectors disposed on a second side of the first package opposite the first side.