# US 2018/0026013 A1 · Memory device including interposer and system-in-package including the same

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- Number: US 2018/0026013 A1
- Document ID: US20180026013A1
- Status: Published application
- Kind: A1
- Application number: 15/612,296
- Filed: 2017-06-02
- Published: 2018-01-25
- Earliest claimed: 2016-07-22
- Inventors: Won-Joo YUN; Sukyong Kang; Hye-Seung Yu; Hyunui Lee
- Web page: https://patentgrep.com/patent/US20180026013A1

## CPC

- H10W 90/00: Package configurations
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 29/26: Accessing multiple arrays (G11C29/24 takes precedence)
- G11C 29/30: Accessing single arrays
- G11C 29/48: Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
- H10W 72/90: Bond pads, in general
- H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads}
- H10W 70/63: Vias, e.g. via plugs
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/07254: {changes in dispositions}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A memory device including an interposer including a first plurality of paths and a second plurality of paths, a first memory die attached to a first surface of the interposer, the first memory die including a first physical layer connected to the first plurality of paths, the first physical layer being attached to a first surface of the interposer, and a second memory die attached to a second surface of the interposer, the second memory die including a second physical layer connected to the second plurality of paths, the second physical layer being attached to a second surface of the interposer, the second physical layer not interfering with the first physical layer in a plan view may be provided.

## Claims

### Claim 1 (depends on 1)

A memory device comprising:
an interposer including a first plurality of paths and a second plurality of paths;
a first memory die attached to a first surface of the interposer, the first memory die including a first physical layer connected to the first plurality of paths, the first physical layer being attached to the first surface of the interposer; and
a second memory die attached to a second surface of the interposer, the second memory die including a second physical layer connected to the second plurality of paths, the second physical layer being attached to the second surface of the interposer, the second physical layer not interfering with the first physical layer in a plan view. The memory device of claim 1, wherein the first physical layer and the second physical layer have a same layout.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the first plurality of paths and the second plurality of paths do not interfere with each other in the plan view.

### Claim 4 (depends on 3)

The memory device of claim 3, wherein the first physical layer and the second physical layer are situated on different planes.

### Claim 5 (depends on 4)

The memory device of claim 4, further comprising:
a first plurality of micro-bumps between the first plurality of paths and the first physical layer; and
a second plurality of micro-bumps between the second plurality of paths and the second physical layer,
wherein the first plurality of micro-bumps and the second plurality of micro-bumps do not interfere with each other in the plan view.

### Claim 6 (depends on 5)

The memory device of claim 5, wherein the first plurality of micro-bumps and the second plurality of micro-bumps are situated on different planes.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein
the first memory die further includes,
a first memory cell array; and
a first test circuit configured to test the first memory cell array, and
the second memory die further includes,
a second memory cell array; and
a second test circuit configured to test the second memory cell array.

### Claim 8 (depends on 7)

The memory device of claim 7, wherein
the first memory die further includes a first plurality of through silicon vias (TSVs),
the second memory die further includes a second plurality of TSVs, and
the memory device further includes,
a third memory die electrically connected to the first plurality of TSVs, and
a fourth memory die electrically connected to the second plurality of TSVs.

### Claim 9 (depends on 8)

The memory device of claim 8, wherein
the third memory die includes a third memory cell array,
the fourth memory die includes a fourth memory cell array,
the first test circuit is further configured to test at least one of the first memory cell array or the third memory cell array, and
the second test circuit is further configured to test at least one of the second memory cell array or the fourth memory cell array.

### Claim 10

A system-in-package comprising:
a processor;
an interposer connected to the processor;
a first memory die attached to a first surface of the interposer, the first memory die including a first physical layer, the first physical layer configured to perform input and output of data to and from the processor; and
a second memory die attached to a second surface of the interposer, the second memory die including a second physical layer, the second physical layer configured to perform input and output of data to and from the processor, the second physical layer not interfering with the first physical layer in a plan view.

### Claim 11 (depends on 10)

The system-in-package of claim 10, wherein the first physical layer and the second physical layer have a same layout.

### Claim 12 (depends on 10)

The system-in-package of claim 10, wherein the interposer comprises:
a first plurality of paths connecting the processor to the first memory die; and
a second plurality of paths connecting the processor to the second memory die, and
wherein the first plurality of paths and the second plurality of paths do not interfere with each other in the plan view.

### Claim 13 (depends on 12)

The system-in-package of claim 12, further comprising:
a first plurality of micro-bumps between the first plurality of paths and the first physical layer; and
a second plurality of micro-bumps between the second plurality of paths and the second physical layer,
wherein the first plurality of micro-bumps and the second plurality of micro-bumps do not interfere with each other in the plan view.

### Claim 14 (depends on 13)

The system-in-package of claim 13, wherein
the first physical layer and the second physical layer are situated on different planes, and
the first plurality of micro-bumps and the second plurality of micro-bumps are situated on different planes.

### Claim 15 (depends on 10)

The system-in-package of claim 10, wherein
first memory die includes a first plurality of through silicon vias (TSVs),
the second memory die further includes a second plurality of TSVs, and
the system-in-package further comprises a third memory die and a fourth die, the third memory die electrically connected to the first plurality of TSVs, and the fourth memory die electrically connected to the second plurality of TSVs,

### Claim 16

A system-in-package comprising:
an interposer including a first plurality of paths and a second plurality of paths, the interposer including a top surface and a bottom surface;
a processor die at a first side of the interposer, the processor die attached to one of the top surface or the bottom surface of the interposer at the first side of the interposer, the processor connected to both the first plurality of paths and the second plurality of paths;
a first memory die at a second side of the interposer, the second side opposite to the first side, the first memory die attached to the top surface of the interposer, the first memory die including a first physical layer connected to the first plurality of paths; and
a second memory die at the second side of the interposer, the second memory die attached to the bottom surface of the interposer, the second memory die including a second physical layer connected to the second plurality of paths, the second plurality of paths not overlapping the first plurality of paths in a plan view.

### Claim 17 (depends on 16)

The system-in-package of claim 16, wherein the first physical layer do not overlap the second physical layer in the plan view.

### Claim 18 (depends on 16)

The system-in-package of claim 16, wherein the first physical layer includes a first plurality of input/output pads, and the second physical layer includes a second plurality of input/output pads.

### Claim 19 (depends on 18)

The system-in-package of claim 18, wherein the first plurality of input/output pads and the second plurality of input/output pads are alternately arranged in the plan view.

### Claim 20 (depends on 16)

The system-in-package of claim 16, wherein at least a portion of the interposer includes a flexible material.