# US 2018/0026010 A1 · Package structure and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0026010 A1 - Document ID: US20180026010A1 - Status: Published application - Kind: A1 - Application number: 15/215,605 - Filed: 2016-07-21 - Published: 2018-01-25 - Earliest claimed: 2016-07-21 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Li-Hsien Huang; An-Jhih Su; Hsien-Wei Chen; Hua-Wei Tseng; Jo-Mei Wang; Tien-Chung Yang; Kuan-Chung Lu - Web page: https://patentgrep.com/patent/US20180026010A1 ## CPC - H10W 90/00: Package configurations - H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons - H10W 42/276: {the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation} - H10W 70/092: {Adapting interconnections, e.g. making engineering changes, repairing} - H10W 70/095: {of vias therein} - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/611: {for connecting multiple chips together} - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/635: {Through-vias} - H10W 70/641: {Adaptable interconnections, e.g. fuses or antifuses} - H10W 70/65: Shapes or dispositions of interconnections - H10W 74/016: {using moulds} - H10W 74/129: {forming a chip-scale package [CSP]} - H10W 42/271: {the arrangements being between stacked chips} - H10W 46/00: Marks applied to devices, e.g. for alignment or identification - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip} - H10W 72/874: {On different surfaces} - H10W 72/9413: {on encapsulations} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/20: Configurations of stacked chips - H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A package structure has first and second dies, a molding compound, a first redistribution layer, at least one first through interlayer via (TIV), second through interlayer vias (TIVs), an electromagnetic interference shielding layer and conductive elements. The first die is molded in the molding compound. The second die is disposed on the molding compound. The first redistribution layer is located between the conductive elements and the molding compound and electrically connected to the first and second dies. The molding compound is located between the second die and the first redistribution layer. The first and second TIVs are molded in the molding compound and electrically connected to the first redistribution layer. The second TIVs are located between the first die and the first TIV. The electromagnetic interference shielding layer is in contact with the first TIV. The conductive elements are connected to the first redistribution layer. ## Claims ### Claim 1 A package structure, comprising: at least one first die, molded in a molding compound; at least one second die, disposed on the molding compound; a first redistribution layer, disposed on the molding compound and electrically connected to the first die and the second die, wherein the molding compound is located between the second die and the first redistribution layer; at least one first through interlayer via, molded in the molding compound and electrically connected to the first redistribution layer; second through interlayer vias, molded in the molding compound and electrically connected to the first redistribution layer, wherein the second through interlayer vias are located between the first die and the first through interlayer via; an electromagnetic interference shielding layer, disposed over the second die and in contact with the first through interlayer via; and conductive elements, connected to the first redistribution layer, wherein the first redistribution layer is located between the conductive elements and the molding compound. ### Claim 2 (depends on 1) The package structure as claimed in claim 1, further comprising a sealing material disposed between the second die and the molding compound, wherein the electromagnetic interference shielding layer penetrating through the sealing material to be in contact with the first through interlayer. ### Claim 3 (depends on 1) The package structure as claimed in claim 1, wherein the electromagnetic interference shielding layer is in contact with the sealing material, the molding compound and the first redistribution layer. ### Claim 4 (depends on 1) The package structure as claimed in claim 1, further comprising connectors being in contact with the second through interlayer vias and the second die, wherein the second die is electrically connected to the first redistribution layer through the connectors and the second through interlayer vias. ### Claim 5 (depends on 1) The package structure as claimed in claim 1, wherein the first die comprises conductive pillars, and the first die is electrically connected to the first redistribution layer through the conductive pillars. ### Claim 6 (depends on 1) The package structure as claimed in claim 1, further comprising a sealing element disposed in the first redistribution layer, wherein the sealing element is at least partially overlapped with the first through interlayer via. ### Claim 7 (depends on 1) The package structure as claimed in claim 1, further comprising a patterned dielectric layer located between the first die and the second die and having a plurality of openings, wherein the first die is disposed on the patterned dielectric layer through a die attached film, and a portion of the first through interlayer via is correspondingly located in one of the opening. ### Claim 8 (depends on 1) The package structure as claimed in claim 1, wherein the second die is stacked over the first die and located between the electromagnetic interference shielding layer and the molding compound. ### Claim 9 A package structure, comprising: a first die, molded in a molding compound; a first redistribution layer, disposed on the molding compound and electrically connected to the first die; at least one through via, molded in the molding compound and electrically connected to the first redistribution layer; a second die, disposed on the molding compound and electrically connected to the first redistribution layer, wherein the molding compound is located between the second die and the first redistribution layer; a sealing material disposed on the molding compound and located between the second die and the molding compound, wherein the sealing material has at least one contact window exposing the through via; an electromagnetic interference shielding layer, disposed over the second die, wherein the electromagnetic interference shielding layer is in contact with the through via through the contact window; and conductive elements, connected to the first redistribution layer, wherein the first redistribution layer is located between the conductive elements and the molding compound. ### Claim 10 (depends on 9) The package structure as claimed in claim 9, further comprising through interlayer vias molded in the molding compound and electrically connected to the first redistribution layer, wherein the through interlayer vias are located between the first die and the through via. ### Claim 11 (depends on 10) The package structure as claimed in claim 10, further comprising connectors being in contact with the through interlayer vias and the second die, wherein the second die is electrically connected to the first redistribution layer through the connectors and the through interlayer vias. ### Claim 12 (depends on 9) The package structure as claimed in claim 9, wherein the first die comprises conductive pillars, and the first die is electrically connected to the first redistribution layer through the conductive pillars. ### Claim 13 (depends on 9) The package structure as claimed in claim 9, further comprising a sealing element disposed in the first redistribution layer, wherein the sealing element is at least partially overlapped with the through via. ### Claim 14 (depends on 9) The package structure as claimed in claim 9, further comprising a patterned dielectric layer located between the first die and the second die and having a plurality of openings, wherein the first die is disposed on the patterned dielectric layer, and a portion of the through via is correspondingly located in one of the opening. ### Claim 15 A method of manufacturing a package structure, comprising: disposing a first die on a car er; forming at least one first through interlayer via on the carrier; encapsulating the first die and the first through interlayer via in a molding compound; forming a first redistribution layer on the molding compound, wherein the first redistribution layer is electrically connected to the first die and the first through interlayer via; disposing conductive elements on the first redistribution layer, wherein the first redistribution layer is located between the molding compound and the conductive elements; debonding the carrier from the first die and the first through interlayer via; disposing a second die on the molding compound, wherein the second die is electrically connected to the first redistribution layer, and the molding compound is located between the second die and the first redistribution layer; disposing a sealing material between the second die and the molding compound; forming at least one contact window exposing the first through interlayer via by performing a laser drilling on the sealing material; and forming an electromagnetic interference shielding layer over the second die, wherein the electromagnetic interference shielding layer is in contact with the first through interlayer via through the contact window. ### Claim 16 (depends on 15) The method as claimed in claim 15, further comprising forming second through interlayer vias on the carrier, wherein the second through interlayer vias are encapsulated inside the molding compound and located between the first die and the first through interlayer via, and the second through interlayer vias are electrically connected to the first redistribution layer. ### Claim 17 (depends on 16) The method as claimed in claim 16, wherein the first through interlayer via and the second through interlayer vias are simultaneously formed. ### Claim 18 (depends on 16) The method as claimed in claim 16, wherein disposing the second die further comprises disposing connectors to directly contact the second through interlayer vias and the second die, wherein the second die is electrically connected to the first redistribution layer through the connectors and the second through interlayer vias ### Claim 19 (depends on 18) The method as claimed in claim 18, wherein the second die is connected to the second through interlayer vias through flip chip bonding technology. ### Claim 20 (depends on 15) The method as claimed in claim 15, wherein the electromagnetic interference shielding layer is formed in a conformal manner.