# US 2018/0025998 A1 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0025998 A1 - Document ID: US20180025998A1 - Status: Published application - Kind: A1 - Application number: 15/719,634 - Filed: 2017-09-29 - Published: 2018-01-25 - Earliest claimed: 2015-12-18 - Assignees: Renesas Electronics Corporation - Applicants: Renesas Electronics Corporation - Inventors: Shuuichi KARIYAZAKI - Web page: https://patentgrep.com/patent/US20180025998A1 ## CPC - H10W 44/601: {Capacitive arrangements (H10W44/20 takes precedence)} - H05K 1/0231: {Capacitors or dielectric substances} - H10W 20/495: {Capacitive arrangements or effects of, or between wiring layers} - H10W 44/20: at high-frequency [HF] or radio frequency [RF] - H10W 70/611: {for connecting multiple chips together} - H10W 70/65: Shapes or dispositions of interconnections - H10W 72/00: Interconnections or connectors in packages - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H05K 1/181: associated with surface mounted components - H05K 2201/10378: Interposers - H10W 44/216: {Waveguides, e.g. strip lines} - H10W 44/241: {for passive devices or passive elements} - H10W 70/63: Vias, e.g. via plugs - H10W 70/635: {Through-vias} - H10W 70/685: comprising multiple insulating layers - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ## Abstract A semiconductor device with enhanced performance. The semiconductor device has a high speed transmission path which includes a first coupling part to couple a semiconductor chip and an interposer electrically, a second coupling part to couple the interposer and a wiring substrate, and an external terminal formed on the bottom surface of the wiring substrate. The high speed transmission path includes a first transmission part located in the interposer to couple the first and second coupling parts electrically and a second transmission part located in the wiring substrate to couple the second coupling part and the external terminal electrically. The high speed transmission path is coupled with a correction circuit in which one edge is coupled with a branching part located midway in the second transmission part and the other edge is coupled with a capacitative element, and the capacitative element is formed in the interposer. ## Claims ### Claim 1 A semiconductor device comprising: a first substrate having a first front surface and a first back surface opposite to the first front surface; a second substrate having a second front surface and a second back surface opposite to the second front surface and being mounted over the first substrate with the first front surface of the first substrate facing the second back surface; and a first semiconductor component mounted over the second front surface of the second substrate and coupled with a first signal transmission path, the first signal transmission path comprising: a first coupling part to couple the first semiconductor component and the second substrate electrically; a second coupling part to couple the second substrate and the first substrate; a first external terminal formed on the first back surface of the first substrate; a first transmission part located in the second substrate to couple the first coupling part and the second coupling part electrically; and a second transmission part located in the first substrate to couple the second coupling part and the first external terminal electrically, wherein the first signal transmission path is coupled with a first circuit part having one edge coupled with a first branching part located midway in the second transmission part and the other edge coupled with a first capacitative element, and wherein the first capacitative element is formed in the second substrate. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the first substrate and the second substrate each have a plurality of conductor patterns, and wherein arrangement density of the conductor patterns in the second substrate is higher than arrangement density of the conductor patterns in the first substrate. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein wiring path distance of the first transmission part is shorter than wiring path distance of the second transmission part. ### Claim 4 (depends on 3) The semiconductor device according to claim 3, wherein the first substrate comprises a first core insulating layer, a first through hole wiring penetrating the first core insulating layer in a thickness direction, and a first through hole land coupled with the first through hole wiring, and wherein an area of a first electrode configuring the first capacitative element is smaller than an area of the first through hole land. ### Claim 5 (depends on 3) The semiconductor device according to claim 3, wherein the first substrate comprises a first core insulating layer, a first through hole wiring penetrating the first core insulating layer in a thickness direction, a first wiring layer lying between the first core insulating layer and the first front surface, and a second wiring layer lying between the first core insulating layer and the first back surface, and wherein the first branching part of the first signal transmission path is formed in the first wiring layer of the first substrate. ### Claim 6 (depends on 5) The semiconductor device according to claim 5, wherein the second substrate comprises a second core insulating layer, a second through hole wiring penetrating the second core insulating layer in the thickness direction, a third wiring layer lying between the second core insulating layer and the second front surface, and a fourth wiring layer lying between the second core insulating layer and the second back surface, and wherein a first electrode configuring the first capacitative element in the first circuit part is formed in the fourth wiring layer of the second substrate. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein the second substrate has a plurality of wiring layers, and wherein a first electrode configuring the first capacitative element is formed in the wiring layers of the second substrate and coupled through a via wiring to couple the wiring layers electrically. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein a first electrode configuring the first capacitative element is a conductor pattern with a larger width than a width of a wiring configuring the second transmission part of the first substrate. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, a first electrode configuring the first capacitative element being a conductor pattern comprising: a first edge located on a side of the first branching part; a second edge located opposite to the first edge and spaced from a conductor pattern other than the first electrode; and an extending part to couple the first edge and the second edge. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, wherein the first substrate and the second substrate each have a plurality of wiring layers, and wherein distance between adjacent wiring layers in a thickness direction among the wiring layers of the second substrate is shorter than distance between adjacent wiring layers in a thickness direction among the wiring layers of the first substrate. ### Claim 11 (depends on 10) The semiconductor device according to claim 10, wherein the first substrate comprises a first core insulating layer, a first through hole wiring penetrating the first core insulating layer in the thickness direction, and a first through hole land coupled with the first through hole wiring, and wherein an area of a first electrode configuring the first capacitative element is smaller than an area of the first through hole land. ### Claim 12 (depends on 1) The semiconductor device according to claim 1, the first semiconductor component being coupled with not only the first signal transmission path but also a second signal transmission path, the second signal transmission path comprising: a third coupling part to couple the first semiconductor component and the second substrate electrically; a fourth coupling part to couple the second substrate and the first substrate; a second external terminal formed on the first back surface of the first substrate; a third transmission part located in the second substrate to couple the third coupling part and the fourth coupling part electrically; and a fourth transmission part located in the first substrate to couple the fourth coupling part and the second external terminal electrically, wherein a second capacitative element is coupled with a wiring path of the third transmission part of the second signal transmission path. ### Claim 13 (depends on 12) The semiconductor device according to claim 12, wherein wiring path distance of the third transmission part is longer than wiring path distance of the first transmission part. ### Claim 14 (depends on 13) The semiconductor device according to claim 13, wherein wiring path distance of the fourth transmission part is shorter than wiring path distance of the second transmission part. ### Claim 15 (depends on 1) The semiconductor device according to claim 1, the second substrate comprising: a semiconductor substrate having the second back surface and a main surface opposite to the second back surface; a wiring layer lying between the main surface and the second front surface; and a plurality of through electrodes penetrating from one of the main surface and the second back surface of the semiconductor substrate to the other, the first capacitative element of the first circuit part comprising: a first conductor pattern electrically coupled with the first signal transmission path through a first through electrode among the through electrodes and formed in the wiring layer. ### Claim 16 (depends on 15) The semiconductor device according to claim 15, the first capacitative element of the first circuit part comprising: a second conductor pattern which extends from the main surface of the semiconductor substrate toward the second back surface and is electrically coupled with the first signal transmission path through the first conductor pattern. ### Claim 17 (depends on 1) The semiconductor device according to claim 1, wherein a second semiconductor component electrically coupled with the first semiconductor component through a plurality of second signal transmission paths is mounted over the second front surface of the second substrate, wherein the second substrate comprises a first core insulating layer, a plurality of first through hole wirings penetrating the first core insulating layer in a thickness direction, a first wiring layer lying between the first core insulating layer and the second front surface, and a second wiring layer lying between the first core insulating layer and the second back surface, wherein the second signal transmission paths are not formed in the first through hole wirings and the second wiring layer, and wherein a first electrode configuring the first capacitative element of the first circuit part is formed in the second wiring layer of the second substrate. ### Claim 18 A semiconductor device comprising: a first substrate having a first front surface and a first back surface opposite to the first front surface; a second substrate having a second front surface and a second back surface opposite to the second front surface and being mounted over the first substrate with the first front surface of the first substrate facing the second back surface; a first semiconductor component mounted over the second front surface of the second substrate and coupled with a plurality of first signal transmission paths; and a second semiconductor component mounted over the second front surface of the second substrate and electrically coupled with the first semiconductor component through a plurality of second signal transmission paths, the first signal transmission paths each comprising: a first coupling part to couple the first semiconductor component and the second substrate electrically; a second coupling part to couple the second substrate and the first substrate; a first external terminal formed on the first back surface of the first substrate; a first transmission part located in the second substrate to couple the first coupling part and the second coupling part electrically; and a second transmission part located in the first substrate to couple the second coupling part and the first external terminal electrically, wherein each of the first signal transmission paths is coupled with a first circuit part having one edge coupled with a first branching part located midway in the second transmission part and the other edge coupled with a first capacitative element, wherein the second substrate comprises a first core insulating layer, a plurality of first through hole wirings penetrating the first core insulating layer in the thickness direction, a first wiring layer lying between the first core insulating layer and the second front surface, and a second wiring layer lying between the first core insulating layer and the second back surface, wherein the second signal transmission paths are not formed in the first through hole wirings and the second wiring layer, and wherein a first electrode configuring the first capacitative element of the first circuit part is formed in the second wiring layer of the second substrate.