# US 2018/0025997 A1 · Semicondcutor structure and semiconductor manufacturing process thereof

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- Number: US 2018/0025997 A1
- Document ID: US20180025997A1
- Status: Published application
- Kind: A1
- Application number: 15/214,463
- Filed: 2016-07-20
- Published: 2018-01-25
- Earliest claimed: 2016-07-20
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yu-Chia Lai; Chen-Hua Yu; Chang-Pin Huang; Chung-Shi Liu; Hsien-Ming Tu; Hung-Yi Kuo; Hao-Yi Tsai; Shih-Wei Liang; Ren-Xuan Liu
- Web page: https://patentgrep.com/patent/US20180025997A1

## CPC

- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 20/42: Vias, e.g. via plugs
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/90: Bond pads, in general
- H10W 74/017: {Auxiliary layers for moulds, e.g. release layers or layers preventing residue}
- H10W 74/141: {the encapsulations being on at least the sidewalls of the semiconductor body}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure has an integrated circuit component, a conductive contact pad, a seal ring structure, a conductive via, a ring barrier, and a mold material. The conductive contact pad is disposed on and electrically connected with the integrated circuit component. The seal ring structure is disposed on the integrated circuit component and surrounding the conductive contact pad. The conductive via is disposed on and electrically connected with the conductive contact pad. The ring barrier is disposed on the seal ring structure. The ring barrier surrounds the conductive via. The mold material covers side surfaces of the integrated circuit component. A semiconductor manufacturing process is also provided.

## Claims

### Claim 1

A semiconductor structure comprising:
an integrated circuit;
a conductive contact pad, disposed on and electrically connected with the integrated circuit;
a seal ring structure, disposed on the integrated circuit and surrounding the conductive contact pad;
a conductive via, disposed on and electrically connected with the conductive contact pad;
a ring barrier, disposed on top of the seal ring structure, wherein the seal ring structure and the ring barrier are distributed within a first side and second side of the integrated circuit, and the ring barrier surrounds the conductive via; and
a mold material covering side surfaces of the integrated circuit.

### Claim 2 (depends on 1)

The semiconductor structure as claimed in claim 1, wherein a height of the conductive via is substantially the same as a height of the ring barrier.

### Claim 3 (depends on 1)

The semiconductor structure as claimed in claim 1, further comprising:
a first passivation layer, disposed on the integrated circuit, wherein the conductive contact pad and seal ring structure are disposed on the first passivation layer, and the first passivation layer comprises at least one opening exposing the integrated circuit; and
a second passivation layer, disposed on the first passivation layer and covering a portion of the seal ring structure and a portion of the conductive contact pad, wherein the second passivation layer comprises a plurality of openings exposing the seal ring structure and the conductive contact pad.

### Claim 4 (depends on 3)

The semiconductor structure as claimed in claim 3, further comprising a dielectric layer, disposed on the mold material and the second passivation layer, wherein the dielectric layer includes a plurality of openings exposing the ring barrier and the conductive via;
a redistribution layer, disposed on the dielectric layer, the ring barrier, and the conductive via, wherein the redistribution layer includes at least one contact pad electrically connected to the ring barrier and the conductive via; and
at least one conductive terminal, disposed on the at least one contact pad.

### Claim 5 (depends on 1)

The semiconductor structure as claimed in claim 1, wherein the mold material covers side surfaces of the ring barrier.

### Claim 6 (depends on 1)

The semiconductor structure as claimed in claim 1, wherein a width of the ring barrier is greater than a width of the seal ring structure.

### Claim 7 (depends on 1)

The semiconductor structure as claimed in claim 1, wherein a height of the ring barrier is greater than a height of the seal ring.

### Claim 8

A semiconductor structure comprising:
an integrated circuit;
a first passivation layer, disposed on the integrated circuit;
a first patterned conductive layer, disposed on the first passivation layer, wherein the first patterned conductive layer comprises:
a conductive contact pad, electrically connected to the integrated circuit; and
a seal ring structure surrounding the conductive contact pad;
a second passivation layer, disposed on the first passivation layer and covering the first patterned conductive layer, wherein the second passivation layer comprises at least one first opening exposing the conductive contact pad;
a second patterned conductive layer, disposed on the second passivation layer, wherein the second patterned conductive layer comprises:
a conductive via, electrically connected to the conductive contact pad; and
a ring barrier, disposed on top of the seal ring structure, wherein the seal ring structure and the ring barrier are distributed within a first side and second side of the integrated circuit, and the ring barrier surrounds the conductive via; and
a mold material covering side surfaces of the integrated circuit.

### Claim 9 (depends on 8)

The semiconductor structure as claimed in claim 8, wherein the second passivation layer further comprises at least one second opening exposing the seal ring structure.

### Claim 10 (depends on 8)

The semiconductor structure as claimed in claim 8, wherein a height of the conductive via is substantially the same as a height of the ring barrier.

### Claim 11 (depends on 8)

The semiconductor structure as claimed in claim 8, further comprising a dielectric layer, disposed on the mold material and the second passivation layer, wherein the dielectric layer includes a plurality of third openings exposing the ring barrier and the conductive via;
a redistribution layer, disposed on the dielectric layer, the ring barrier, and the conductive via, wherein the redistribution layer includes at least one contact pad electrically connected to the ring barrier and the conductive via; and
at least one conductive terminal, disposed on the at least one contact pad.

### Claim 12 (depends on 8)

The semiconductor structure as claimed in claim 8, wherein the mold material covers side surfaces of the ring barrier.

### Claim 13 (depends on 8)

The semiconductor structure as claimed in claim 8, wherein a width of the ring barrier is larger than a width of the seal ring structure.

### Claim 14 (depends on 8)

The semiconductor structure as claimed in claim 8, wherein a height of the ring barrier is greater than a height of the seal ring.

### Claim 15

A semiconductor manufacturing process comprising:
forming a first passivation layer on a wafer having at least one integrated circuit, wherein the first passivation layer comprises at least one opening exposing the at least one integrated circuit;
forming a first patterned conductive layer on the first passivation layer, wherein the first patterned conductive layer comprises at least one seal ring structure and at least one conductive contact pad, the at least one conductive contact pad is electrically connected to the at least one integrated circuit, and the at least one seal ring structure surrounds the at least one conductive contact pad;
forming a second passivation layer on the first patterned conductive layer and the first passivation layer;
forming a second patterned conductive layer on the second passivation layer, wherein the second patterned conductive layer comprises at least one conductive via and at least one ring barrier, the at least one conductive via is electrically connected to the at least one conductive contact pad, the at least one ring barrier is disposed on top of the at least one seal ring structure, the at least one seal ring structure and the at least one ring barrier are distributed within a first side and second side of the integrated circuit, and the at least one ring barrier surrounds the at least one conductive via.

### Claim 16 (depends on 15)

The process as claimed in claim 15, wherein the second patterned conductive layer is formed through plating such that a height of the at least one conductive via is substantially the same as a height of the at least one ring barrier.

### Claim 17 (depends on 15)

The process as claimed in claim 15, further comprising:
mounting the at least one integrated circuit on a carrier;
disposing a release film on the second patterned conductive layer;
forming a molding material on the carrier encapsulating sidewalls of the at least one integrated circuit;
removing the release film;
forming a dielectric layer on the molding material and exposing the second patterned conductive layer;
forming a redistribution layer on the dielectric layer and the second patterned conductive layer, wherein the redistribution layer comprises at least one contact pad electrically connected to the second patterned conductive layer; and
disposing at least one conductive terminal on the at least one contact pad.

### Claim 18 (depends on 17)

The process as claimed in claim 17, wherein in the step of forming the molding material on the carrier, the molding material encapsulates sidewalls of the at least one ring barrier.

### Claim 19 (depends on 15)

The process as claimed in claim 15, wherein in the step of forming the second passivation layer, the second passivation layer is patterned to comprise at least one first opening exposing the at least one conductive contact pad and at least one second opening exposing the seal ring structure.

### Claim 20 (depends on 15)

The process as claimed in claim 15, wherein a height of the ring barrier is greater than a height of the seal ring.