# US 2018/0025995 A1 · Reducing wafer warpage during wafer processing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0025995 A1 - Document ID: US20180025995A1 - Status: Published application - Kind: A1 - Application number: 15/722,524 - Filed: 2017-10-02 - Published: 2018-01-25 - Earliest claimed: 2015-03-12 - Assignees: Toshiba Memory Corporation - Applicants: Toshiba Memory Corporation - Inventors: Kenji KONOMI - Web page: https://patentgrep.com/patent/US20180025995A1 ## CPC - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10P 54/00: Cutting or separating of wafers, substrates or parts of devices - H10P 58/00: Singulating wafers or substrates into multiple chips, i.e. dicing - H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract According to one embodiment, there is provided a manufacturing method of a semiconductor device. The method includes forming a first guard ring around a first chip region on a semiconductor wafer. The method includes forming a second guard ring around a second chip region on the semiconductor wafer. The method includes mechanically connecting the first guard ring with the second guard ring through a joist structure. ## Claims ### Claim at position 1 1: A manufacturing method of a semiconductor device comprising: forming a first guard ring around a first chip region on a semiconductor wafer; forming a second guard ring around a second chip region on the semiconductor wafer; and mechanically connecting the first guard ring with the second guard ring through a joist structure. ### Claim at position 2 (depends on 1) 2: The manufacturing method of the semiconductor device according to claim 1, wherein the connecting through the joist structure further comprises connecting a first portion with a second portion through a number of connection patterns, the first portion being a portion extending along the second guard ring in the first guard ring, the second portion being a portion extending along the first guard ring. ### Claim at position 3 (depends on 2) 3: The manufacturing method of the semiconductor device according to claim 2, wherein a number of the connection patterns are formed of a material having a tensile stress or a compressive stress according to a warping state of the semiconductor wafer. ### Claim at position 4 (depends on 2) 4: The manufacturing method of the semiconductor device according to claim 2, wherein the connecting through the joist structure further comprises connecting the first portion with the second portion through a number of the connection patterns not to overlap a mark pattern arranged between the first portion and the second portion. ### Claim at position 5 (depends on 2) 5: The manufacturing method of the semiconductor device according to claim 2, wherein the connecting through the joist structure further comprises connecting one end side of the first portion with one end side of the second portion through a first connection pattern, connecting another end side of the first portion with another end side of the second portion through a second connection pattern, and connecting the first portion with the second portion through a third connection pattern between the first connection pattern and the second connection pattern. ### Claim at position 6 (depends on 5) 6: The manufacturing method of the semiconductor device according to claim 5, wherein each of the first connection pattern, the second connection pattern, and the third connection pattern extends obliquely to a longitudinal direction of the first portion. ### Claim at position 7 (depends on 5) 7: The manufacturing method of the semiconductor device according to claim 5, wherein the connecting through the joist structure further comprises connecting the one end side of the first portion with the one end side of the second portion through a fourth connection pattern to intersect with the first connection pattern, connecting the other end side of the first portion with the other end side of the second portion through a fifth connection pattern to intersect with the second connection pattern, and connecting the first portion with the second portion through a sixth connection pattern between the first connection pattern and the second connection pattern to intersect with the third connection pattern. ### Claim at position 8 (depends on 7) 8: The manufacturing method of the semiconductor device according to claim 7, wherein the first connection pattern and the fourth connection pattern form substantially a letter X shape at a planar view, the second connection pattern and the fifth connection pattern form substantially a letter X shape at a planar view, and the third connection pattern and the sixth connection pattern form substantially a letter X shape at a planar view. ### Claim at position 9 (depends on 5) 9: The manufacturing method of the semiconductor device according to claim 5, wherein an interval between the first connection pattern and the third connection pattern in a longitudinal direction of the first portion is equivalent to an interval between the third connection pattern and the second connection pattern in the longitudinal direction of the first portion. ### Claim at position 10 (depends on 5) 10: The manufacturing method of the semiconductor device according to claim 5, wherein the joist structure is formed to have a same layer structure as the guard ring. ### Claim at position 11 11-20. (canceled)