# US 2018/0025992 A1 · Semiconductor package structure and manufacturing method thereof

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- Number: US 2018/0025992 A1
- Document ID: US20180025992A1
- Status: Published application
- Kind: A1
- Application number: 15/371,869
- Filed: 2016-12-07
- Published: 2018-01-25
- Earliest claimed: 2016-07-25
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: JUI-PIN HUNG; FENG-CHENG HSU; SHUO-MAO CHEN; SHIN-PUU JENG; DE-DUI MARVIN LIAO
- Web page: https://patentgrep.com/patent/US20180025992A1

## CPC

- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- G06F 16/24: Querying
- G06F 16/435: Filtering based on additional data, e.g. user or group profiles
- G06F 16/9535: Search customisation based on user profiles and personalisation
- G06Q 10/40: Business processes related to social networking or social networking services
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/095: {of vias therein}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 72/00: Interconnections or connectors in packages
- H10W 74/016: {using moulds}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 90/00: Package configurations
- G06Q 99/00: Subject matter not provided for in other groups of this subclass
- H10P 72/7418: {of passive members, e.g. a chip mounting substrate}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/63: Vias, e.g. via plugs
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06Q: INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package structure includes a redistribution layer (RDL), a chip, a plurality of interconnecting bumps and an encapsulant. The redistribution layer has a first surface and a second surface opposite to each other. The chip is disposed over the redistribution layer with a plurality of contact pads facing the first surface and electrically connected to the redistribution layer. The interconnecting bumps are disposed over the first surface and electrically connected to the redistribution layer. The encapsulant is disposed over the first surface of the redistribution layer, and the encapsulant encloses the chip and surrounds lateral walls of the interconnecting bumps.

## Claims

### Claim at position 1

1: A semiconductor package structure, comprising:
a redistribution layer (RDL) having a first surface and a second surface opposite to each other;
a chip disposed over the redistribution layer with a plurality of contact pads facing the first surface and electrically connected to the redistribution layer;
a plurality of interconnecting bumps disposed over the first surface and electrically connected to the redistribution layer;
a second chip disposed over the second surface and electrically connected to the redistribution layer; and
an encapsulant disposed over the first surface of the redistribution layer, wherein the encapsulant encloses the chip and surrounds lateral walls of the interconnecting bumps.

### Claim at position 2 (depends on 1)

2: The semiconductor package structure of claim 1, further comprising a circuit board disposed over the second surface of the redistribution layer, and a plurality of external connectors disposed between the second surface and the circuit board to electrically connect the redistribution layer with the circuit board.

### Claim at position 3 (depends on 1)

3: The semiconductor package structure of claim 1, further comprising a package disposed over the encapsulant and electrically connected to the redistribution layer through the interconnecting bumps.

### Claim at position 4 (depends on 1)

4: The semiconductor package structure of claim 1, wherein each of the plurality of interconnecting bumps is a solder ball, and two opposite terminals of each of the plurality of interconnecting bumps are exposed from the encapsulant.

### Claim at position 5 (depends on 1)

5: The semiconductor package structure of claim 1, wherein the chip comprises an active device chip and a passive device chip.

### Claim 6

(canceled)

### Claim at position 7

7: A semiconductor package structure, comprising:
a first redistribution layer (RDL) having a first surface and a second surface opposite to each other;
a first chip disposed over the first redistribution layer with a plurality of contact pads facing the first surface and electrically connected to the first redistribution layer;
a plurality of first interconnecting bumps disposed over the first surface and electrically connected to the first redistribution layer;
a first encapsulant disposed over the first surface of the first redistribution layer, wherein the first encapsulant encloses the first chip and surrounds lateral walls of the first interconnecting bumps;
a second redistribution layer over the second surface of the first redistribution layer, wherein the second redistribution layer has a third surface and a fourth surface opposite to each other, and the third surface facing the second surface;
a second chip disposed over the second redistribution layer with a plurality of contact pads facing the third surface;
a plurality of second interconnecting bumps disposed over the third surface and electrically connected to the second redistribution layer; and
a second encapsulant disposed between the first redistribution layer and the second redistribution layer, wherein the second encapsulant encloses the second chip and surrounds lateral walls of the second interconnecting bumps.

### Claim at position 8 (depends on 7)

8: The semiconductor package structure of claim 7, further comprising a circuit board disposed over the fourth surface of the second redistribution layer, and a plurality of external connectors disposed between the fourth surface and the circuit board to electrically connect the second redistribution layer with the circuit board.

### Claim at position 9 (depends on 7)

9: The semiconductor package structure of claim 7, further comprising a package disposed over the first encapsulant and electrically connected to the first redistribution layer through the first interconnecting bumps.

### Claim at position 10 (depends on 7)

10: The semiconductor package structure of claim 7, wherein each of the plurality of first interconnecting bumps is a solder ball, and two opposite terminals of each of the plurality of first interconnecting bumps are exposed from the first encapsulant.

### Claim at position 11 (depends on 7)

11: The semiconductor package structure of claim 7, wherein each of the plurality of second interconnecting bumps is a solder ball, and two opposite terminals of each of the plurality of second interconnecting bumps are exposed from the second encapsulant.

### Claim at position 12 (depends on 7)

12: The semiconductor package structure of claim 7, further comprising a plurality of conductive posts disposed in the second encapsulant, wherein each of the plurality of conductive posts is a solder paste, one terminal of each of the plurality of conductive posts is connected to the second redistribution layer, and the other terminal of each of the plurality of conductive posts is connected to the corresponding second interconnecting bump.

### Claim at position 13 (depends on 7)

13: The semiconductor package structure of claim 7, wherein the first chip comprises a memory chip and a passive device chip.

### Claim at position 14 (depends on 7)

14: The semiconductor package structure of claim 7, wherein the second chip comprises an active device chip and a passive device chip.

### Claim at position 15 (depends on 7)

15: The semiconductor package structure of claim 7, further comprising a third chip disposed over the fourth surface and electrically connected to the second redistribution layer.

### Claim at position 16

16-20. (canceled)

### Claim at position 17

21: A semiconductor package structure, comprising:
a redistribution layer (RDL) having a first surface and a second surface opposite to each other;
a chip disposed over the redistribution layer with a plurality of contact pads facing the first surface and electrically connected to the redistribution layer;
a plurality of interconnecting bumps disposed over the first surface and electrically connected to the redistribution layer;
a plurality of conductive posts disposed over the first surface, wherein one terminal of each of the plurality of conductive posts is connected to the redistribution layer, and the other terminal of each of the plurality of conductive posts is connected to the corresponding interconnecting bump; and
an encapsulant disposed over the first surface of the redistribution layer, wherein the encapsulant encloses the chip and surrounds lateral walls of the interconnecting bumps and lateral walls of the conductive posts.

### Claim at position 18 (depends on 21)

22: The semiconductor package structure of claim 21, further comprising a circuit board disposed over the second surface of the redistribution layer, and a plurality of external connectors disposed between the second surface and the circuit board to electrically connect the redistribution layer with the circuit board.

### Claim at position 19 (depends on 21)

23: The semiconductor package structure of claim 21, further comprising a package disposed over the encapsulant and electrically connected to the redistribution layer through the interconnecting bumps and the conductive posts.

### Claim at position 20 (depends on 21)

24: The semiconductor package structure of claim 21, wherein the chip comprises an active device chip and a passive device chip.

### Claim at position 21 (depends on 21)

25: The semiconductor package structure of claim 21, further comprising a second chip disposed over the second surface and electrically connected to the redistribution layer.

### Claim at position 22 (depends on 1)

26: The semiconductor package structure of claim 1, further comprising a second redistribution layer over the second surface of the redistribution layer, wherein the second redistribution layer has a third surface and a fourth surface opposite to each other, the third surface faces the second surface, and the second chip includes a plurality of contact pads facing the third surface of the second redistribution layer.