# US 2018/0025991 A1 · Semiconductor device and a method of manufacturing the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2018/0025991 A1
- Document ID: US20180025991A1
- Status: Published application
- Kind: A1
- Application number: 15/709,733
- Filed: 2017-09-20
- Published: 2018-01-25
- Earliest claimed: 2008-02-14
- Assignees: Renesas Electronics Corporation
- Applicants: Renesas Electronics Corporation
- Inventors: Masami KOKETSU; Toshiaki SAWADA
- Web page: https://patentgrep.com/patent/US20180025991A1

## CPC

- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics}
- H10D 86/60: wherein the TFTs are in active matrices
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/30: Die-attach connectors
- H10W 46/101: {characterised by the type of information, e.g. logos or symbols}
- H10W 46/301: {for alignment}
- H10W 46/603: {Formed on wafers or substrates before dicing and remaining on chips after dicing}
- H10W 72/07223: {Active alignment, e.g. using optical alignment using marks or sensors}
- H10W 72/07237: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy}
- H10W 72/07251: {characterised by changes in properties of the bump connectors during connecting}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07331: {Connecting techniques}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.

## Claims

### Claim at position 1

1-28. (canceled)

### Claim 29

A semiconductor device comprising:
a semiconductor substrate;
an integrated circuit region in which a plurality of MISFETs are formed;
an alignment mark region in which an alignment mark is formed;
a first wiring layer formed over the integrated circuit region and the alignment mark region;
a second wiring layer formed over the first wiring layer; and
a plurality of STI regions formed in the semiconductor substrate and in the alignment mark region,
wherein the first wiring layer comprises:
a plurality of first wirings formed in the integrated circuit region, and which are electrically coupled to the plurality of MISFETs; and
a plurality of dummy wiring regions formed in the alignment mark region, and which are not electrically coupled to the plurality of MISFETs,
wherein the second wiring layer comprises:
the alignment mark formed in the alignment mark region; and
a plurality of second wirings formed in the integrated circuit region,
wherein the plurality of dummy wiring regions comprises:
a first dummy wiring region disposed to overlap with the alignment mark; and
a second dummy wiring region disposed to not overlap with the alignment mark, and
wherein the plurality of STI regions comprises:
a first STI region disposed to overlap with the alignment mark; and
a second STI region disposed to not overlap with the alignment mark.

### Claim 30 (depends on 29)

A semiconductor device according to claim 29,
wherein the second wiring layer is an uppermost layer of a plurality of wiring layers of the semiconductor device.

### Claim 31 (depends on 29)

A semiconductor device according to claim 29,
wherein the dummy wiring regions are not connected to any of other wirings respectively.

### Claim 32 (depends on 29)

A semiconductor device according to claim 29,
wherein a planar area size of each one of the dummy wiring regions is smaller than that of the alignment mark, and
wherein a planar area size of each one of the STI regions is smaller than that of the alignment mark.

### Claim 33 (depends on 29)

A semiconductor device according to claim 29, further comprising:
a bump electrode formed over the second wiring layer and electrically connected to any one of the second wirings.

### Claim 34 (depends on 29)

A semiconductor device according to claim 29,
wherein the plurality of first dummy wiring regions and the plurality of STI regions are arranged so as to be shifted respectively in a plan view.

### Claim 35 (depends on 29)

A semiconductor device according to claim 29,
wherein the respective first dummy wiring regions are dot-shaped.