# US 2018/0025990 A1 · Prevention of premature breakdown of interline porous dielectrics in an integrated circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0025990 A1 - Document ID: US20180025990A1 - Status: Published application - Kind: A1 - Application number: 15/722,703 - Filed: 2017-10-02 - Published: 2018-01-25 - Earliest claimed: 2015-10-01 - Assignees: STMicroelectronics (Rousset) SAS - Applicants: STMicroelectronics (Rousset) SAS - Inventors: Christian Rivero; Pascal Fornara; Jean-Philippe Escales - Web page: https://patentgrep.com/patent/US20180025990A1 ## CPC - H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants - H10P 14/6905: {being a silicon carbide or silicon carbonitride and not containing oxygen, e.g. SiC or SiC:H} - H10W 20/056: {by filling conductive material into holes, grooves or trenches} - H10W 20/074: {of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers} - H10W 20/076: {in via holes or trenches} - H10W 20/42: Vias, e.g. via plugs - H10W 20/43: Layouts of interconnections - H10W 20/4421: {the principal metal being copper} - H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A non-porous dielectric barrier is provided between a porous portion of a dielectric region and an electrically conductive element of an interconnect portion of an integrated circuit. This non-porous dielectric barrier protects the integrated circuit from breakdown of the least one dielectric region caused by electrical conduction assisted by the presence of defects located in the at least one dielectric region. ## Claims ### Claim 1 A process, comprising: forming two electrically conductive elements of an interconnect portion of an integrated circuit that are separated from each other by a porous portion of a dielectric region; and inserting at least one non-porous dielectric barrier between the porous portion of said dielectric region and at least one of the two electrically conductive elements to protect the integrated circuit from electrical conduction assisted by the presence of defects located in the dielectric region separating the two electrically conductive elements; wherein inserting comprises providing the at least one non-porous dielectric barrier along a side wall of the porous portion of the dielectric region but not extending along a bottom surface of said at least one of the two electrically conductive elements. ### Claim 2 (depends on 1) The process according to claim 1, wherein inserting comprises inserting two non-porous dielectric barriers along side walls of the porous portion of the dielectric region respectively between said porous portion and said two electrically conductive elements but not extending along bottom surfaces of either of said two electrically conductive elements. ### Claim 3 (depends on 1) The process according to claim 1, wherein said porous portion of the dielectric region has a degree of porosity higher than or equal to a first threshold and the non-porous dielectric barrier has a degree of porosity lower than a second threshold. ### Claim 4 (depends on 3) The process according to claim 3, wherein the first threshold is equal to the second threshold. ### Claim 5 (depends on 3) The process according to claim 3, wherein the first threshold and the second threshold are equal to within 5%. ### Claim 6 (depends on 1) The process according to claim 1, wherein said porous portion of the dielectric region includes a low-dielectric-constant material. ### Claim 7 (depends on 6) The process according to claim 6, wherein a dielectric constant of said low-dielectric-constant material is lower than or equal to 3.5. ### Claim 8 (depends on 1) The process according to claim 1, wherein the porous portion of the dielectric region contains porous hydrogenated silicon oxycarbide. ### Claim 9 (depends on 1) The process according to claim 1, wherein said at least one non-porous dielectric barrier has a thickness comprised between 10 nm and 30 nm. ### Claim 10 (depends on 1) The process according to claim 1, wherein said at least one non-porous dielectric barrier comprises silicon carbonitride. ### Claim 11 (depends on 1) The process according claim 1, wherein the two electrically conductive elements include metal lines of a given metallization level of said interconnect portion. ### Claim 12 (depends on 1) The process according claim 1, wherein the two electrically conductive elements include vias below a given metallization level of said interconnect portion. ### Claim 13 A process, comprising: forming an opening in a porous material dielectric region, said opening having a side wall and a bottom wall; depositing a non-porous dielectric barrier on said side wall and said bottom wall; completely removing a portion of the non-porous dielectric barrier along the bottom wall; filling the opening with metal material to form an electrically conductive element that is laterally separated from an upper portion of the porous material dielectric region by the non-porous dielectric barrier along the side wall but is in contact with a lower portion of the porous material dielectric region along the bottom wall. ### Claim 14 (depends on 13) The method according to claim 13, wherein forming the opening comprises forming a first opening and a second opening, and wherein depositing the non-porous dielectric barrier comprises depositing the non-porous dielectric barrier on side walls and bottom walls of the first and second openings, and wherein completely removing comprises completely removing portions of the non-porous dielectric barrier along the bottom walls. ### Claim 15 (depends on 13) The process according to claim 13, wherein said porous material dielectric region has a degree of porosity higher than or equal to a first threshold and the non-porous dielectric barrier has a degree of porosity lower than a second threshold. ### Claim 16 (depends on 15) The process according to claim 15, wherein the first threshold is equal to the second threshold. ### Claim 17 (depends on 15) The process according to claim 15, wherein the first threshold and the second threshold are equal to within 5%. ### Claim 18 (depends on 13) The process according to claim 13, wherein said porous material dielectric region is made of a low-dielectric-constant material. ### Claim 19 (depends on 18) The process according to claim 18, wherein a dielectric constant of said low-dielectric-constant material is lower than or equal to 3.5. ### Claim 20 (depends on 13) The process according to claim 13, wherein the porous material dielectric region contains porous hydrogenated silicon oxycarbide. ### Claim 21 (depends on 13) The process according to claim 13, wherein said at least one non-porous dielectric barrier has a thickness comprised between 10 nm and 30 nm. ### Claim 22 (depends on 13) The process according to claim 13, wherein said at least one non-porous dielectric barrier comprises silicon carbonitride. ### Claim 23 (depends on 13) The process according claim 13, wherein the electrically conductive element is a metal line of an interconnect metallization level. ### Claim 24 (depends on 13) The process according claim 13, wherein the electrically conductive element is a via below an interconnect metallization level.