# US 2018/0025987 A1 · Wafer-Level Packaged Components and Methods Therefor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0025987 A1 - Document ID: US20180025987A1 - Status: Published application - Kind: A1 - Application number: 15/393,048 - Filed: 2016-12-28 - Published: 2018-01-25 - Earliest claimed: 2016-07-22 - Assignees: Invensas Corporation - Applicants: Invensas Corporation - Inventors: Min Tao; Hoki Kim; Ashok S. Prabhu; Zhuowen Sun; Wael Zohni; Belgacem Haba - Web page: https://patentgrep.com/patent/US20180025987A1 ## CPC - H10W 90/00: Package configurations - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/095: {of vias therein} - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/611: {for connecting multiple chips together} - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/635: {Through-vias} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/685: comprising multiple insulating layers - H10W 72/071: {Connecting or disconnecting} - H10W 72/073: {of die-attach connectors} - H10W 72/50: Bond wires - H10W 72/90: Bond pads, in general - H10W 74/016: {using moulds} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation} - H10W 74/129: {forming a chip-scale package [CSP]} - H10W 74/131: {the semiconductor body being only partially enclosed} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/63: Vias, e.g. via plugs - H10W 70/655: Fan-out layouts - H10W 70/681: {comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/59: Bond pads specially adapted therefor - H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip} - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 90/20: Configurations of stacked chips - H10W 90/288: {characterised by arrangements for thermal management of the stacked chips} - H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips} - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/752: {between stacked chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Wafer-level packaged components are disclosed. In a wafer-level-packaged, an integrated circuit die has first contacts in an inner third region of a surface of the integrated circuit die. A redistribution layer has second contacts in an inner third region of a first surface of the redistribution layer and third contacts in an outer third region of a second surface of the redistribution layer opposite the first surface thereof. The second contacts of the redistribution layer are coupled for electrical conductivity to the first contacts of the integrated circuit die with the surface of the integrated circuit die face-to-face with the first surface of the redistribution layer. The third contacts are offset from the second contacts for being positioned in a fan-out region for association at least with the outer third region of the second surface of the redistribution layer, the third contacts being surface mount contacts. ## Claims ### Claim 1 A wafer-level packaged microelectronic component, comprising: an integrated circuit die of a wafer having first contacts in an inner third region of a surface of the integrated circuit die; a first redistribution layer having second contacts in an inner third region of a first surface of the first redistribution layer and third contacts in an outer third region of a second surface of the first redistribution layer opposite the first surface thereof; the second contacts of the first redistribution layer coupled for electrical conductivity to the first contacts of the integrated circuit die with the surface of the integrated circuit die face-to-face with the first surface of the redistribution layer; a second redistribution layer having fourth contacts in an inner third region of a first surface of the second redistribution layer and interconnects in an outer third region of a second surface of the second redistribution layer opposite the first surface thereof; and the third contacts offset from the second contacts for being positioned in a fan-out region for association at least with the outer third region of the second surface of the first redistribution layer, the third contacts being surface mount contacts. ### Claim 2 (depends on 1) The microelectronic component according to claim 1, wherein: the first contacts and the second contacts correspond to one another; and the inner third region of each of the surface of the integrated circuit die and the first surface of the first redistribution layer correspond to one another. ### Claim 3 (depends on 2) The microelectronic component according to claim 2, wherein only the third contacts are externally available for interconnection on the first surface of the first redistribution layer. ### Claim 4 (depends on 1) The microelectronic component according to claim 1, wherein the integrated circuit die is part of a die stack. ### Claim 5 (depends on 1) The microelectronic component according to claim 1, wherein the surface of the integrated circuit die is a first surface thereof, the microelectronic component further comprising: the integrated circuit die having through die vias in an outer third region of the first surface thereof and a second surface opposite the first surface thereof; the interconnects of the second redistribution layer coupled for electrical conductivity to the through die vias of the integrated circuit die with the second surface of the integrated circuit die face-to-face with the second surface of the second redistribution layer; and the interconnects offset from the fourth contacts for being positioned in the fan-out region for association at least with the outer third region of the second surface of the second redistribution layer. ### Claim 6 (depends on 5) The microelectronic component according to claim 5, wherein the integrated circuit die is a first integrated circuit die, the microelectronic component further comprising: a second integrated circuit die having fifth contacts in an inner third region of a surface of the second integrated circuit die; and the fourth contacts of the second redistribution layer coupled for electrical conductivity to the fifth contacts of the second integrated circuit die with the surface of the second integrated circuit die face-to-face with the first surface of the second redistribution layer. ### Claim 7 A method for forming a wafer-level packaged microelectronic component, comprising: obtaining an integrated circuit die of a wafer having first contacts in an inner third region of a surface of the integrated circuit die; wafer-level processing to form a first redistribution layer on the surface of the integrated circuit die, the first redistribution layer formed to have: second contacts in an inner third region of a first surface of the first redistribution layer interconnected to the first contacts of the integrated circuit die with the surface of the integrated circuit die face-to-face with the first surface of the first redistribution layer; third contacts in an outer third region of a second surface of the first redistribution layer opposite the first surface thereof coupled for electrical conductivity to the second contacts; and the third contacts offset from the second contacts for being positioned in a fan-out region for association at least with the outer third region of the second surface of the first redistribution layer, the third contacts being surface mount contacts; and wafer-level processing to form a second redistribution layer having fourth contacts in an inner third region of a first surface of the second redistribution layer and interconnects in an outer third region of a second surface of the second redistribution layer opposite the first surface thereof. ### Claim 8 (depends on 7) The method according to claim 7, wherein: the first contacts and the second contacts correspond to one another; and the inner third region of each of the surface of the integrated circuit die and the first surface of the first redistribution layer correspond to one another. ### Claim 9 (depends on 8) The method according to claim 8, wherein only the third contacts are externally available for interconnection on the second surface of the first redistribution layer ### Claim 10 (depends on 7) The method according to claim 7, wherein the integrated circuit die is part of a die stack. ### Claim 11 A method for forming a wafer-level packaged microelectronic component, comprising: obtaining an integrated circuit die of a wafer having first contacts in an inner third region of a first surface of the integrated circuit die; wafer-level processing to form a first redistribution layer on the first surface of the integrated circuit die, the first redistribution layer formed to have: second contacts in an inner third region of a first surface of the first redistribution layer interconnected to the first contacts of the integrated circuit die with the first surface of the integrated circuit die face-to-face with the first surface of the first redistribution layer; third contacts in an outer third region of a second surface of the first redistribution layer opposite the first surface thereof coupled for electrical conductivity to the second contacts; and the third contacts offset from the second contacts for being positioned in a fan-out region for association at least with the outer third region of the second surface of the first redistribution layer, the third contacts being surface mount contacts; wafer-level processing to form a second redistribution layer on a second surface of the integrated circuit die opposite the first surface thereof, the second redistribution layer formed to have fourth contacts in an inner third region of a first surface of the second redistribution layer and interconnects in an outer third region of a second surface of the second redistribution layer opposite the first surface thereof; the integrated circuit die having through die vias in an outer third region of the first surface and a second surface opposite the first surface; the interconnects of the second redistribution layer coupled for electrical conductivity to the through die vias of the integrated circuit die with the second surface of the integrated circuit die face-to-face with the second surface of the second redistribution layer; and the interconnects offset from the fourth contacts for being positioned in the fan-out region for association at least with the outer third region of the second surface of the second redistribution layer. ### Claim 12 (depends on 11) The method according to claim 11, wherein: the first contacts and the second contacts correspond to one another; and the inner third region of each of the surface of the integrated circuit die and the first surface of the redistribution layer correspond to one another. ### Claim 13 (depends on 12) The method according to claim 12, wherein only the third contacts are externally available for interconnection on the second surface of the redistribution layer ### Claim 14 (depends on 11) The method according to claim 11, wherein the integrated circuit die is part of a die stack. ### Claim 15 (depends on 11) The method according to claim 11, wherein the integrated circuit die is a first integrated circuit die, the method further comprising: obtaining a second integrated circuit die having fifth contacts in an inner third region of a surface of the second integrated circuit die; and surface mounting the second integrated circuit die for having the fourth contacts of the second redistribution layer coupled for electrical conductivity to the fifth contacts of the second integrated circuit die with the surface of the second integrated circuit die face-to-face with the first surface of the second redistribution layer. ### Claim 16 A wafer-level packaged microelectronic component, comprising: an integrated circuit die of a wafer having first contacts in an inner third region of a first surface of the integrated circuit die and through die vias in an outer third region of the first surface of the integrated circuit die; a first redistribution layer having second contacts in an inner third region of a first surface of the first redistribution layer and first interconnects in an outer third region of a second surface of the first redistribution layer opposite the first surface thereof; the first interconnects of the first redistribution layer coupled for electrical conductivity to the through substrate vias of the integrated circuit die with a second surface of the integrated circuit die opposite the first surface thereof face-to-face with the second surface of the first redistribution layer; a second redistribution layer having third contacts in an inner third region of a first surface of the second redistribution layer and second interconnects in an outer third region of a second surface of the second redistribution layer opposite the first surface thereof; and the second contacts offset from the first interconnects for being positioned in a fan-out region for association at least with the outer third region of the second surface of the first redistribution layer, the second contacts being surface mount contacts. ### Claim 17 (depends on 16) The microelectronic component according to claim 16, wherein the inner third region of each of the first surface of the integrated circuit die and the first surface of the first redistribution layer correspond to one another. ### Claim 18 (depends on 16) The microelectronic component according to claim 16, wherein the integrated circuit die is a first integrated circuit die, the microelectronic component further comprising: a second integrated circuit die having fourth contacts in an inner third region of a surface of the second integrated circuit die; and the third contacts of the second redistribution layer coupled for electrical conductivity to the fourth contacts of the second integrated circuit die with the surface of the second integrated circuit die face-to-face with the first surface of the second redistribution layer. ### Claim 19 A method for forming a wafer-level packaged microelectronic component, comprising: obtaining an integrated circuit die of a wafer having first contacts in an inner third region of a first surface of the integrated circuit die and through die vias in an outer third region of the first surface of the integrated circuit die; and wafer-level processing to form a first redistribution layer on the first surface of the integrated circuit die, the first redistribution layer formed to have: second contacts in an inner third region of a first surface of the first redistribution layer and first interconnects in an outer third region of a second surface of the first redistribution layer opposite the first surface thereof; the first interconnects of the first redistribution layer coupled for electrical conductivity to the through substrate vias of the integrated circuit die with a second surface of the integrated circuit die opposite the first surface thereof face-to-face with the second surface of the first redistribution layer; and the second contacts offset from the first interconnects for being positioned in a fan-out region for association at least with the outer third region of the second surface of the first redistribution layer, the second contacts being surface mount contacts; and wafer-level processing to form a second redistribution layer having third contacts in an inner third region of a first surface of the second redistribution layer and second interconnects in an outer third region of a second surface of the second redistribution layer opposite the first surface thereof. ### Claim 20 (depends on 19) The method according to claim 19, wherein the integrated circuit die is a first integrated circuit die, the method further comprising: obtaining a second integrated circuit die having fourth contacts in an inner third region of a surface of the second integrated circuit die; and coupling the third contacts of the second redistribution layer for electrical conductivity to the fourth contacts of the second integrated circuit die with the surface of the second integrated circuit die face-to-face with the first surface of the second redistribution layer.