# US 2018/0025985 A1 · Fan-out package structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0025985 A1 - Document ID: US20180025985A1 - Status: Published application - Kind: A1 - Application number: 15/498,542 - Filed: 2017-04-27 - Published: 2018-01-25 - Earliest claimed: 2016-07-22 - Assignees: Mediatek Inc. - Applicants: Mediatek Inc. - Inventors: Min-Chen LIN; Che-Ya CHOU; Nan-Cheng CHEN - Web page: https://patentgrep.com/patent/US20180025985A1 ## CPC - H10W 70/65: Shapes or dispositions of interconnections - H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons - H10W 44/20: at high-frequency [HF] or radio frequency [RF] - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/611: {for connecting multiple chips together} - H10W 74/141: {the encapsulations being on at least the sidewalls of the semiconductor body} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 44/248: {for antennas} - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/63: Vias, e.g. via plugs - H10W 70/685: comprising multiple insulating layers - H10W 72/072: {of bump connectors} - H10W 72/073: {of die-attach connectors} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/9413: {on encapsulations} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/00: Package configurations - H10W 90/10: Configurations of laterally-adjacent chips - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/729: {between a chip and a laterally-adjacent discrete passive device} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package structure including a redistribution layer (RDL) structure having a first surface and a second surface opposite thereto is provided. The RDL structure includes an inter-metal dielectric (IMD) layer and a first conductive layer disposed at a first layer-level of the IMD layer. A molding compound covers the first surface of the RDL structure. A first semiconductor die is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure. A plurality of bump structures is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure. ## Claims ### Claim 1 A semiconductor package structure, comprising: a redistribution layer (RDL) structure having a first surface and a second surface opposite thereto, wherein the RDL structure comprises an inter-metal dielectric (IMD) layer and a first conductive layer disposed at a first layer-level of the IMD layer; a molding compound covering the first surface of the RDL structure; a first semiconductor die disposed over the second surface of the RDL structure and electrically coupled to the RDL structure; and a plurality of bump structures disposed over the second surface of the RDL structure and electrically coupled to the RDL structure. ### Claim 2 (depends on 1) The semiconductor package structure as claimed in claim 1, further comprising an underfill layer interposed between the second surface of the RDL structure and the first semiconductor die. ### Claim 3 (depends on 1) The semiconductor package structure as claimed in claim 1, further comprising a second semiconductor die and an electronic component disposed within the molding compound, arranged side-by-side, and electrically coupled to the RDL structure. ### Claim 4 (depends on 3) The semiconductor package structure as claimed in claim 3, wherein the electronic component comprises a capacitor, an inductor, a resistor, or a combination thereof. ### Claim 5 (depends on 3) The semiconductor package structure as claimed in claim 3, wherein the second semiconductor die comprises a radio frequency front-end component, an integrated passive device, or a combination thereof. ### Claim 6 (depends on 3) The semiconductor package structure as claimed in claim 3, wherein the first conductive layer has a ground shielding pattern. ### Claim 7 (depends on 3) The semiconductor package structure as claimed in claim 3, wherein the first conductive layer has an antenna pattern that is laterally spaced apart from the first semiconductor die, the second semiconductor die, and the electronic component, as viewed from a top-view aspect. ### Claim 8 A semiconductor package structure, comprising: a redistribution layer (RDL) structure having a first surface and a second surface opposite thereto, wherein the RDL structure comprises: an inter-metal dielectric (IMD) layer; a first conductive layer disposed at a first layer-level of the IMD layer; and a second conductive layer disposed at a second layer-level below the first layer-level of the IMD layer; a molding compound covering the first surface of the RDL structure; a first semiconductor die disposed over the second surface of the RDL structure and electrically coupled to the RDL structure; and a plurality of bump structures disposed over the second surface of the RDL structure and electrically coupled to the RDL structure. ### Claim 9 (depends on 8) The semiconductor package structure as claimed in claim 8, further comprising a second semiconductor die and an electronic component disposed within the molding compound, arranged side-by-side, and electrically coupled to the RDL structure. ### Claim 10 (depends on 9) The semiconductor package structure as claimed in claim 9, wherein the electronic component comprises a capacitor, an inductor, a resistor, or a combination thereof. ### Claim 11 (depends on 9) The semiconductor package structure as claimed in claim 9, wherein the second semiconductor die comprises a radio frequency front-end component, an integrated passive device, or a combination thereof. ### Claim 12 (depends on 8) The semiconductor package structure as claimed in claim 8, wherein the first conductive layer has a ground shielding pattern. ### Claim 13 (depends on 8) The semiconductor package structure as claimed in claim 8, wherein the first conductive layer has an antenna pattern that is laterally spaced apart from the first semiconductor die, the second semiconductor die, and the electronic component, as viewed from a top-view aspect. ### Claim 14 A semiconductor package structure, comprising: a redistribution layer (RDL) structure having a first surface and a second surface opposite thereto, wherein the RDL structure comprises: an inter-metal dielectric (IMD) layer; a first conductive layer disposed at a first layer-level of the IMD layer, wherein the first conductive layer has an antenna pattern; a second conductive layer disposed at a second layer-level below the first layer-level of the IMD layer, wherein the second conductive layer has a ground shielding pattern; and a third conductive layer disposed at a third layer-level below the second layer-level of the IMD layer; a molding compound covering the first surface of the RDL structure; a first semiconductor die disposed over the second surface of the RDL structure and electrically coupled to the RDL structure; and a plurality of bump structures disposed over the second surface of the RDL structure and electrically coupled to the RDL structure. ### Claim 15 (depends on 14) The semiconductor package structure as claimed in claim 14, further comprising a second semiconductor die and an electronic component disposed within the molding compound, arranged side-by-side, and electrically coupled to the RDL structure. ### Claim 16 (depends on 15) The semiconductor package structure as claimed in claim 15, wherein the electronic component comprises a capacitor, an inductor, a resistor, or a combination thereof. ### Claim 17 (depends on 15) The semiconductor package structure as claimed in claim 15, wherein the second semiconductor die comprises a radio frequency front-end component, an integrated passive device, or a combination thereof. ### Claim 18 (depends on 15) The semiconductor package structure as claimed in claim 15, wherein the ground shielding pattern is disposed underneath the antenna pattern and entirely covers a surface of the first semiconductor die and the antenna pattern is laterally spaced apart from the second semiconductor die, as viewed from a top-view aspect. ### Claim 19 (depends on 14) The semiconductor package structure as claimed in claim 14, further comprising a second semiconductor die and an electronic component disposed over the second surface of the RDL structure, arranged side-by-side, and electrically coupled to the RDL structure. ### Claim 20 (depends on 19) The semiconductor package structure as claimed in claim 19, wherein the electronic component comprises a capacitor, an inductor, a resistor, or a combination thereof. ### Claim 21 (depends on 19) The semiconductor package structure as claimed in claim 19, wherein the second semiconductor die comprises a radio frequency front-end component, an integrated passive device, or a combination thereof. ### Claim 22 (depends on 19) The semiconductor package structure as claimed in claim 19, wherein the ground shielding pattern is disposed underneath the antenna pattern and entirely covers surfaces of the first semiconductor die and the second semiconductor die, as viewed from a top-view aspect.