# US 2018/0025984 A1 · Semiconductor device having structure for improving voltage drop and device including the same

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- Number: US 2018/0025984 A1
- Document ID: US20180025984A1
- Status: Published application
- Kind: A1
- Application number: 15/721,020
- Filed: 2017-09-29
- Published: 2018-01-25
- Earliest claimed: 2015-07-16
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: SUNG SU BYUN
- Web page: https://patentgrep.com/patent/US20180025984A1

## CPC

- H10W 20/427: {Power or ground buses}
- H10W 20/42: Vias, e.g. via plugs
- H10P 14/40: of conductive or resistive materials
- H10W 20/43: Layouts of interconnections
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/48: Insulating materials thereof
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a semiconductor substrate and a plurality of metal layers above the semiconductor substrate. A first of the metal layers includes a plurality of first power rails which extend in a first direction and provide a first voltage, a plurality of second power rails which extend in the first direction and provide a second voltage, and a first conductor which is integral with one end of each of the first power rails and extends in a second direction. The first direction is perpendicular to the second direction. The first voltage is one of a ground voltage and a power source voltage and the second voltage is the other voltage.

## Claims

### Claim 1

A system-on-chip comprising:
a processor; and
a hardware component connected to the processor,
wherein at least one of the processor and the hardware component comprises:
a semiconductor substrate; and
a plurality of metal layers formed above the semiconductor substrate, and
wherein a first metal layer among the plurality of metal layers comprises:
a plurality of first power rails which extend in a first direction and transmit a first voltage;
a plurality of second power rails which extends in the first direction and transmit a second voltage; and
a first conductor which is coupled to one end of each of the first power rails and extends in a second direction.

### Claim 2 (depends on 1)

The system-on-chip of claim 1,
wherein the first direction is perpendicular to the second direction, the first voltage is one of a ground voltage and an operating voltage, and the second voltage is another of the ground voltage and the operating voltage.

### Claim 3 (depends on 1)

The system-on-chip of claim 1,
wherein a second metal layer placed over the first metal layer comprises:
a third power rail transmitting the first voltage; and
a fourth power rail transmitting the second voltage,
wherein the at least one of the processor and the hardware component further comprises:
a plurality of first vias which connect the first power rails with the third power rail; and
a plurality of second vias which connect the second power rails with the fourth power rail.

### Claim 4 (depends on 1)

The system-on-chip of claim 1,
wherein the first metal layer further comprises a second conductor which is coupled to another end of each of the first power rails and extends in the second direction.

### Claim 5 (depends on 4)

The system-on-chip of claim 4,
wherein the first conductor is integral with each of the first power rails at the one end of each of the first power rails, respectively, and spans the first power rails in the second direction; and
wherein the second conductor is integral with each of the first power rails at the other end of each of the first power rails, respectively, and spans the first power rails in the second direction.

### Claim 6 (depends on 4)

The system-on-chip of claim 4,
wherein a second metal layer among the plurality of metal layers is disposed above the first metal layer;
wherein a third metal layer among the plurality of metal layers is disposed above the second metal layer;
wherein the plurality of first power rails are dedicated for connection to the first voltage and each extend longitudinally in the first direction;
wherein the plurality of second power rails are dedicated for connection to the second voltage and each extend longitudinally in the first direction;
wherein the first conductor is integral exclusively with each of the first power rails at first ends of the first power rails, respectively, and spans the first power rails in the second direction; and
wherein the second conductor is integral exclusively with each of the first power rails at second ends of the first power rails, respectively, and spans the first power rails in the second direction.

### Claim 7 (depends on 1)

The system-on-chip of claim 1, further comprising:
a first logic gate disposed at an upper portion of the semiconductor substrate and electrically connected to a first one of the first power rails and one of the second power rails; and
a second logic gate disposed at the upper portion of the semiconductor substrate and electrically connected to the one of the second power rails and a second one of the first power rails.

### Claim 8 (depends on 1)

The system-on-chip of claim 1, further comprising:
a second conductor which is coupled to one end of each of the second power rails and extends in the second direction,
wherein the first conductor is integral exclusively with each of the first power rails, and
wherein the second conductor is integral exclusively with each of the first power rails.

### Claim 9 (depends on 8)

The system-on-chip of claim 8,
wherein the plurality of first power rails are aligned parallel in the first direction and coupled perpendicular to the first conductor;
wherein the plurality of second power rails are aligned parallel in the first direction and coupled perpendicular to the first conductor; and
wherein the plurality of first power rails and the plurality of second power rails are aligned parallel in an array in which the plurality of first power rails are disposed alternately with the plurality of second power rails.

### Claim 10 (depends on 9)

The system-on-chip of claim 9,
wherein the first conductor is coupled to each of the first power rails on one side of the array; and
wherein the second conductor is coupled to each of the first power rails on another side of the array.

### Claim 11 (depends on 1)

The system on chip of claim 1, further comprising:
a second metal layer disposed above the first metal layer and including a third power rail dedicated for connection to the first voltage and the plurality of first power rails such that the third power rail provides the first voltage to the first power rails, and a fourth power rail dedicated for connection to the second voltage and the plurality of second power rails such that the fourth power rail provides the second voltage to the second power rails.

### Claim 12 (depends on 11)

The system on chip of claim 11,
wherein each of the third power rail and the fourth power rail extend in the second direction.

### Claim 13 (depends on 11)

The system-on-chip of claim 11, further comprising:
a third metal layer interposed between the first metal layer and the second metal layer.

### Claim 14

A mobile device comprising:
a processor;
a memory configured to communicate with the processor; and
a hardware component configured to communicate with the processor,
wherein at least one of the processor, the memory, and the hardware component comprises:
a semiconductor substrate; and
a plurality of metal layers formed above the semiconductor substrate, and
wherein a first metal layer among the plurality of metal layers comprises:
a plurality of first power rails which extend in a first direction and transmit a first voltage;
a plurality of second power rails which extends in the first direction and transmit a second voltage; and
a first conductor which is coupled to one end of each of the first power rails and extends in a second direction.

### Claim 15 (depends on 14)

The mobile device of claim 14,
wherein a second metal layer placed over the first metal layer comprises:
a third power rail transmitting the first voltage; and
a fourth power rail transmitting the second voltage, and
wherein the at least one of the processor, the memory, and the hardware component further comprises:
a plurality of first vias which connect the first power rails with the third power rail; and
a plurality of second vias which connect the second power rails with the fourth power rail.

### Claim 16 (depends on 14)

The mobile device of claim 14,
wherein the first direction is perpendicular to the second direction, the first voltage is one of a ground voltage and an operating voltage, and the second voltage is another of the ground voltage and the operating voltage.

### Claim 17 (depends on 14)

The mobile device of claim 14, further comprising:
an array of active electronic elements arrayed at an upper portion of the semiconductor substrate parallel to an upper surface of the semiconductor substrate as an array in the first direction and the second directions;
wherein the plurality of first power rails each extend in the first direction across the array of active electronic elements;
wherein the plurality of second power rails each extend in the first direction across the array of active electronic elements;
wherein the first conductor is exclusively integral with each of the first power rails at first ends of the first power rails, respectively, and
wherein each of the active electronic elements is electrically connected to a respective one of the first power rails and a respective one of the second power rails.

### Claim 18 (depends on 17)

The mobile device of claim 17, further comprising:
a second conductor that is exclusively integral with each of the first power rails at second ends of the first power rails, respectively,
wherein a second metal layer placed over the first metal layer comprises:
a third power rail transmitting the first voltage; and
a fourth power rail transmitting the second voltage, and
wherein the third power rail is aligned in the first direction between the second conductor and the array of active electronic elements.

### Claim 19 (depends on 17)

The mobile device of claim 17,
wherein the first and second power rails are disposed alternately in the second direction.

### Claim 20

A mobile device comprising:
a system-on-chip that includes a processor, a memory configured to communicate with the processor, and a hardware component configured to communicate with the processor,
wherein at least one of the processor, the memory, and the hardware component comprises:
a semiconductor substrate; and
a plurality of metal layers formed above the semiconductor substrate, and
wherein a first metal layer among the plurality of metal layers comprises:
a plurality of first power rails which extend in a first direction and transmit a first voltage;
a plurality of second power rails which extends in the first direction and transmit a second voltage; and
a first conductor which is coupled to one end of each of the first power rails and extends in a second direction.