# US 2018/0025983 A1 · Designable channel finfet fuse

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- Number: US 2018/0025983 A1
- Document ID: US20180025983A1
- Status: Published application
- Kind: A1
- Application number: 15/668,230
- Filed: 2017-08-03
- Published: 2018-01-25
- Earliest claimed: 2016-07-20
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Keith E. Fogel; Pouya Hashemi; Shogo Mochizuki; Alexander Reznicek
- Web page: https://patentgrep.com/patent/US20180025983A1

## CPC

- H10W 20/493: {Fuses, i.e. interconnections changeable from conductive to non-conductive}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 86/011: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10P 14/3822: {Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing}
- H10W 74/01: Manufacture or treatment
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

On-chip, doped semiconductor fuse regions compatible with FinFET CMOS fabrication are formed from the channel regions of selected fins. One or more fin dimensions are optionally reduced in selected channel regions of the fins following dummy gate removal, such as height and/or width. The channel regions from which the fuse regions are formed are doped to provide electrical conductivity, amorphized using ion implantation, and then annealed to form substantially polycrystalline fuse regions. Source/drain regions function as terminals for the fuse regions.

## Claims

### Claim 1

A monolithic structure, comprising:
a substrate including a plurality of parallel, monocrystalline semiconductor fins, the fins including one or more channel regions and outer fin portions integral with and adjoining the channel regions;
source/drain regions on the outer fin portions of one or more of the fins, each of the channel regions being adjoined by a pair of the source/drain regions; and
a gate structure adjoining each channel region;
wherein the channel region of at least one of the parallel semiconductor fins includes a substantially polycrystalline, doped fuse region operatively associated with a pair of the source/drain regions.

### Claim 2 (depends on 1)

The monolithic structure of claim 1, wherein the gate structure adjoining the channel region including the doped fuse region includes a dielectric layer adjoining the doped fuse region.

### Claim 3 (depends on 2)

The monolithic structure of claim 2, further including spacers adjoining each of the gate structures, the dielectric layer adjoining a pair of the spacers.

### Claim 4 (depends on 3)

The monolithic structure of claim 3, wherein the source/drain regions include doped epitaxial structures extending from the fin portions and have the same doping type as the fuse region.

### Claim 5 (depends on 4)

The monolithic structure of claim 4, wherein the fuse region has one or more dimensions smaller than corresponding dimensions of the fin portions.

### Claim 6 (depends on 5)

The monolithic structure of claim 5, wherein the one or more dimensions includes width.

### Claim 7 (depends on 1)

The monolithic structure of claim 1, wherein the fuse region consists essentially of doped polycrystalline silicon.

### Claim 8 (depends on 7)

The monolithic structure of claim 7, wherein the at least one semiconductor fin includes a pair of the source/drain regions adjoining the recess and having the same conductivity type as the doped fuse region.

### Claim 9 (depends on 1)

The monolithic structure of claim 1, further including electrically conductive contacts electrically connected to the pair of the source/drain regions.