# US 2018/0025973 A1 · Chip

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- Number: US 2018/0025973 A1
- Document ID: US20180025973A1
- Status: Published application
- Kind: A1
- Application number: 15/715,654
- Filed: 2017-09-26
- Published: 2018-01-25
- Earliest claimed: 2015-04-14
- Assignees: Huawei Technologies Co., Ltd.
- Applicants: Huawei Technologies Co., Ltd.
- Inventors: HuiLi Fu; Xiaodong Zhang; Jyh Rong Lin; Zhiqiang Ma
- Web page: https://patentgrep.com/patent/US20180025973A1

## CPC

- H10W 20/43: Layouts of interconnections
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers}
- H10W 70/635: {Through-vias}
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/0198: {batch processes}
- H10W 72/50: Bond wires
- H10W 90/00: Package configurations
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 20/48: Insulating materials thereof
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 72/072: {of bump connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 90/20: Configurations of stacked chips
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present embodiments provides a chip, including a carrier, a redistribution structure, and multiple packaging function modules, where the multiple packaging function modules each have at least a part wrapped by a colloid, and are fastened to the redistribution structure side by side; the redistribution structure is fastened to the carrier, and the redistribution structure includes one or more redistribution metal layers; the redistribution metal layer communicatively connects the multiple packaging function modules and the carrier. The redistribution structure further includes one or more interconnect metal layers, and the interconnect metal layer is communicatively connected to at least two packaging function modules so as to provide a signal path between the at least two packaging function modules. In the chip, two packaging function modules are placed on the carrier side by side, and a signal path is established between the two packaging function modules by using the redistribution structure.

## Claims

### Claim 1

A chip, comprising:
a carrier;
a redistribution structure fastened to the carrier, wherein the redistribution structure comprises at least one redistribution metal layer; and
multiple packaging function modules, wherein the multiple packaging function modules are at least partially wrapped by a colloid, wherein the multiple packaging function modules are fastened to the redistribution structure side-by-side, wherein the redistribution metal layer communicatively connects the multiple packaging function modules to the carrier, wherein the redistribution structure further comprises at least one interconnect metal layer, and wherein the at least one interconnect metal layer is communicatively connected to at least two packaging function modules to provide a signal path between the at least two packaging function modules.

### Claim 2 (depends on 1)

The chip according to claim 1, wherein a main body of the redistribution structure comprises an insulation material, and wherein the at least one interconnect metal layer and the redistribution metal layer are mutually independent in the main body.

### Claim 3 (depends on 2)

The chip according to claim 2, wherein a bump array is disposed on the main body of the redistribution structure, and wherein the bump array is electrically connected to the carrier and to the redistribution metal layer.

### Claim 4 (depends on 3)

The chip according to claim 3, wherein underfill is filled between the redistribution structure and the carrier, into a gap of the bump array, and around the bump array.

### Claim 5 (depends on 1)

The chip according to claim 1, wherein pins are disposed on the multiple packaging function modules, wherein the pins are arranged between the packaging function modules and the redistribution structure, and wherein the pins are electrically connected to the redistribution metal layer or to the at least one interconnect metal layer.

### Claim 6 (depends on 1)

The chip according to claim 1, wherein a pad or a connector is disposed at a bottom of the carrier.

### Claim 7 (depends on 1)

The chip according to claim 1, wherein sides of the multiple packaging function modules that deviate from the carrier are not wrapped by the colloid.

### Claim 8 (depends on 7)

The chip according to claim 7, wherein surfaces of the sides of the multiple packaging function modules that deviate from the carrier are coated with thermal adhesives, and wherein the chip further comprises a heat sink, wherein the heat sink is attached to the surfaces of the sides of the multiple packaging function modules that deviate from the carrier.

### Claim 9 (depends on 8)

The chip according to claim 8, wherein the heat sink comprises a first part that is attached to top surfaces of the multiple packaging function modules and a second part that surrounds the multiple packaging function modules, wherein the second part of the heat sink is fastened to a surface of the carrier by an adhesive.

### Claim 10 (depends on 1)

The chip according to claim 1, wherein the chip further comprises a ring heat sink, wherein the ring heat sink is disposed around the multiple packaging function modules, and wherein the ring heat sink is fastened to the carrier by an adhesive.

### Claim 11 (depends on 1)

The chip according to claim 1, wherein the at least one interconnect metal layer comprises a first interconnect metal layer and a second interconnect metal layer, wherein a part of the first interconnect metal layer and a part of the second interconnect metal layer are mutually parallel, wherein a reference metal layer is disposed between parallel parts of the first interconnect metal layer and the second interconnect metal layer, and wherein the reference metal layer is insulated from another metal layer in the redistribution structure.

### Claim 12 (depends on 1)

The chip according to claim 1, wherein the multiple packaging function modules are a dies, stack dies, or a packaged chips.

### Claim 13

A method comprising:
cutting a first die from a wafer;
cutting a second die from the wafer;
attaching a redistribution structure to the first die and to the second die;
reconstituting the first die and the second die on a redistribution structure, wherein the redistribution structure comprises at least one redistribution metal layer and at least one interconnect metal layers, and wherein the at least one interconnect metal layer is communicatively connected to the first die and to the second die to provide a signal path between the first die and the second die;
forming a colloid to at least partially wrap the first die and the second die; and
attaching the redistribution structure to a carrier, wherein the redistribution structure communicatively connects the first die and the second die to the carrier.

### Claim 14 (depends on 13)

The method of claim 13, further comprising exposing a side of the redistribution structure by grinding or by removing a temporary carrier.

### Claim 15 (depends on 13)

The method of claim 13, further comprising applying underfill between the redistribution structure and the carrier.

### Claim 16

A chip, comprising:
a carrier;
a redistribution structure fastened to the carrier, wherein the redistribution structure comprises at least one redistribution metal layer, wherein a main body of the redistribution structure comprises an insulation material, wherein the redistribution structure further comprises at least one interconnect metal layers, and wherein the at least one interconnect metal layer and the redistribution metal layer are mutually independent in the main body; and
multiple packaging function modules, wherein the redistribution metal layer communicatively connects the multiple packaging function modules to the carrier, and wherein the at least one interconnect metal layer is communicatively connected to at least two packaging function modules to provide a signal path between the at least two packaging function modules.