# US 2018/0025970 A1 · Integrated circuit (ic) structure for high performance and functional density

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- Number: US 2018/0025970 A1
- Document ID: US20180025970A1
- Status: Published application
- Kind: A1
- Application number: 15/218,488
- Filed: 2016-07-25
- Published: 2018-01-25
- Earliest claimed: 2016-07-25
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Min-Feng Kao; Dun-Nian Yaung; Hsing-Chih Lin; Jen-Cheng Liu; Kuan-Chieh Huang
- Web page: https://patentgrep.com/patent/US20180025970A1

## CPC

- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/8314: {the IGFETs characterised by having gate insulating layers with different properties}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10D 88/101: {comprising components on opposite major surfaces of semiconductor substrates}
- H10P 90/1916: {with separation or delamination along an ion implanted layer, e.g. Smart-cut}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- H10W 20/49: Adaptable interconnections, e.g. fuses or antifuses
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 90/00: Package configurations
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit (IC) provides high performance and high functional density. A first back-end-of-line (BEOL) interconnect structure and a second BEOL interconnect structure are respectively under and over a semiconductor substrate. A first electronic device and a second electronic device are between the semiconductor substrate and respectively a bottom of the first BEOL interconnect structure and a top of the second BEOL interconnect structure. A through substrate via (TSV) extends through the semiconductor substrate, from the first BEOL interconnect structure to the second BEOL interconnect structure. A method for manufacturing the IC is also provided.

## Claims

### Claim 1

An integrated circuit (IC) comprising:
a semiconductor substrate;
a first back-end-of-line (BEOL) interconnect structure and a second BEOL interconnect structure respectively under and over the semiconductor substrate;
a first electronic device and a second electronic device between the semiconductor substrate and respectively a bottom of the first BEOL interconnect structure and a top of the second BEOL interconnect structure;
a through substrate via (TSV) extending through the semiconductor substrate, from the first BEOL interconnect structure to the second BEOL interconnect structure;
a pad structure over and electrically coupled to the second BEOL interconnect structure, wherein the pad structure is at a top surface of the IC; and
a dielectric layer over the semiconductor substrate, wherein the dielectric layer extends continuously from direct contact with the semiconductor substrate to direct contact with the pad structure.

### Claim 2 (depends on 1)

The IC according to claim 1, wherein the first and second BEOL interconnect structures each comprise an interlayer dielectric (ILD) layer, via layers, and wiring layers, wherein the via and wiring layers are alternatingly stacked within the ILD layer, and wherein the second electronic device is defined by at least one of the wiring layers of the second BEOL interconnect structure.

### Claim 3

(canceled)

### Claim 4

An integrated circuit (IC) comprising:
a semiconductor substrate;
a first back-end-of-line (BEOL) interconnect structure and a second BEOL interconnect structure respectively under and over the semiconductor substrate;
a first electronic device and a second electronic device between the semiconductor substrate and respectively a bottom of the first BEOL interconnect structure and a top of the second BEOL interconnect structure, wherein the first electronic device is in a bottom of the semiconductor substrate, between the semiconductor substrate and the first BEOL interconnect structure, and wherein the second electronic device is in a top of the semiconductor, between the semiconductor substrate and the second BEOL interconnect structure; and
a through substrate via (TSV) extending through the semiconductor substrate, from the first BEOL interconnect structure to the second BEOL interconnect structure.

### Claim 5 (depends on 4)

The IC according to claim 4, wherein the second electronic device comprises a pair of source/drain regions and a gate electrode, wherein the source/drain regions are in the top of the semiconductor substrate, and wherein the gate electrode is laterally between the source/drain regions.

### Claim 6 (depends on 5)

The IC according to claim 5, wherein the gate electrode is spaced over the semiconductor substrate by a gate dielectric layer that is arranged over and contacts a top surface of the TSV.

### Claim 7 (depends on 1)

The IC according to claim 1, further comprising:
an epitaxial layer in the second BEOL interconnect structure, wherein the second electronic device is in the epitaxial layer.

### Claim 8 (depends on 7)

The IC according to claim 7, wherein the second BEOL interconnect structure comprises a pair of wiring layers and a via layer, wherein the via layer extends from a wiring layer of the pair to another wiring layer of the pair, and wherein the epitaxial layer is spaced between the wiring layers of the pair.

### Claim 9 (depends on 7)

The IC according to claim 7, wherein the second electronic device comprises a pair of source/drain regions and a gate electrode, wherein the source/drain regions are in a top of the epitaxial layer, and wherein the gate electrode is laterally between the source/drain regions.

### Claim 10 (depends on 1)

The IC according to claim 1, further comprising:
a support structure under the first BEOL interconnect structure; and
a bond interface layer between the support structure and the first BEOL interconnect structure, wherein the bond interface layer bonds the support structure to the first BEOL interconnect structure.

### Claim 11 (depends on 10)

The IC according to claim 10, wherein the support structure comprises:
a second semiconductor substrate; and
a third BEOL interconnect structure over the second semiconductor substrate, wherein the bond interface layer bonds and electrically couples the third BEOL interconnect structure to the first BEOL interconnect structure.

### Claim 12

A method for manufacturing an integrated circuit (IC), the method comprising:
forming a first back-end-of-line (BEOL) interconnect structure and a first electronic device on a bottom of a semiconductor substrate, wherein the first electronic device is between the semiconductor substrate and a bottom of the first BEOL interconnect structure;
forming a through substrate via (TSV) extending through the semiconductor substrate to the first BEOL interconnect structure; and
after the forming of the first BEOL interconnect structure, forming a second BEOL interconnect structure and a second electronic device on a top of the semiconductor substrate, wherein the second BEOL interconnect structure contacts the TSV, wherein the second electronic device is between the semiconductor substrate and a top of the second BEOL interconnect structure, wherein the forming of the second BEOL interconnect structure comprises repeatedly depositing and patterning a conductive layer on the semiconductor substrate.

### Claim 13 (depends on 12)

The method according to claim 12, further comprising:
before forming the TSV, bonding the semiconductor substrate to a bulk substrate of glass or a semiconductor material through the first BEOL interconnect structure.

### Claim 14 (depends on 12)

The method according to claim 12, further comprising:
forming a third back-end-of-line (BEOL) interconnect structure and a third electronic device over a second semiconductor substrate, wherein the third electronic device is between the second semiconductor substrate and a top of the third BEOL interconnect structure; and
before forming the TSV, bonding the semiconductor substrate to the third BEOL interconnect structure through the first BEOL interconnect structure.

### Claim 15 (depends on 12)

The method according to claim 12, wherein forming the second BEOL interconnect structure comprises forming via layers and wiring layers alternatingly stacked, and wherein forming the second electronic device comprises forming at least one of the wiring layers with a layout of the second electronic device.

### Claim 16 (depends on 12)

The method according to claim 12, further comprising:
forming the first and second electronic devices as transistors respectively in the bottom of the semiconductor substrate and the top of the semiconductor substrate.

### Claim 17 (depends on 12)

The method according to claim 12, wherein forming the second BEOL interconnect structure and the second electronic device comprise:
forming a wiring layer over the semiconductor substrate;
forming an epitaxial layer spaced over the wiring layer;
forming the second electronic device in the epitaxial layer; and
forming another wiring layer over the second electronic device.

### Claim 18 (depends on 17)

The method according to claim 17, wherein forming the second BEOL interconnect structure and the second electronic device further comprises forming an interlayer dielectric (ILD) layer covering the wiring layer before forming the epitaxial layer, and wherein forming the epitaxial layer comprises:
implanting ions into a third semiconductor substrate to form an in-depth weakened layer spaced between top and bottom surfaces of the third semiconductor substrate;
bonding the third semiconductor substrate to the ILD layer; and
cleaving the third semiconductor substrate along the in-depth weakened layer to remove part of the third substrate from the ILD layer.

### Claim 19

(canceled)

### Claim 20

(canceled)

### Claim 21 (depends on 1)

The IC according to claim 1, further comprising:
a solder bump overlying and directly contacting the pad structure.

### Claim 22 (depends on 12)

The method according to claim 12, wherein the second BEOL interconnect structure comprises a first wire and a second wire over the first wire, wherein the forming of the second BEOL interconnect structure comprises depositing a first conductive layer covering the semiconductor substrate and the first BEOL interconnect structure, patterning the first conductive layer to define the first wire, depositing a second conductive layer covering the semiconductor substrate and the first wire, and patterning the second conductive layer to define the second wire.

### Claim 23 (depends on 12)

The method according to claim 12, wherein the first BEOL interconnect structure is formed directly on the bottom of the semiconductor substrate, and wherein the second BEOL interconnect structure is formed directly on the top of the semiconductor substrate.