# US 2018/0025967 A1 · Flip-chip, face-up and face-down centerbond memory wirebond assemblies

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- Number: US 2018/0025967 A1
- Document ID: US20180025967A1
- Status: Published application
- Kind: A1
- Application number: 15/715,725
- Filed: 2017-09-26
- Published: 2018-01-25
- Earliest claimed: 2011-04-21
- Assignees: Tessera, Inc.
- Applicants: Tessera, Inc.
- Inventors: Belgacem Haba; Richard Dewitt Crisp; Wael Zohni
- Web page: https://patentgrep.com/patent/US20180025967A1

## CPC

- H10W 72/00: Interconnections or connectors in packages
- H10W 70/68: Shapes or dispositions thereof
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/00: Package configurations
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 70/40: Leadframes
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/655: Fan-out layouts
- H10W 70/656: Fan-in layouts
- H10W 70/681: {comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage}
- H10W 70/685: comprising multiple insulating layers
- H10W 72/251: {Materials}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/354: {comprising polymers}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/5366: {the bond wires having kinks}
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/5473: {multiple bond wires connected to a common bond pad}
- H10W 72/551: {Materials of bond wires}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/856: {Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15)}
- H10W 72/865: {Die-attach connectors and bond wires}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 72/951: {Materials of bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/231: {the stacked chips being on both top and bottom sides of an auxiliary carrier having no electrical connection structure}
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/752: {between stacked chips}
- H10W 90/753: {between laterally-adjacent chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A microelectronic assembly can include a substrate having first and second surfaces and an aperture extending therebetween, the substrate having terminals. The assembly can also include a first microelectronic element having a front surface facing the first surface of the substrate, a second microelectronic element having a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, first and second leads electrically connecting contacts of the respective first and second microelectronic elements to the terminals, and third leads electrically interconnecting the contacts of the first and second microelectronic elements. The contacts of the first microelectronic element can be exposed at the front surface thereof adjacent the edge thereof. The contacts of the second microelectronic element can be disposed in a central region of the front surface thereof. The first, second, and third leads can have portions aligned with the aperture.

## Claims

### Claim 1

A microelectronic assembly, comprising:
a substrate having oppositely-facing first and second surfaces and an aperture extending between the first and second surfaces, the substrate having terminals;
a first microelectronic element having a front surface facing the first surface of the substrate, a rear surface remote therefrom, and an edge extending between the front and rear surfaces, the first microelectronic element having a plurality of contacts exposed at the front surface thereof adjacent the edge of the first microelectronic element;
a second microelectronic element having first and second opposed edges, a front surface extending between the first and second edges, and a plurality of contacts disposed in a central region of the front surface thereof remote from the first and second edges, the front surface of the second microelectronic element facing the first microelectronic element and projecting beyond the edge of the first microelectronic element;
first leads electrically connecting the contacts of the first microelectronic element to the terminals;
second leads electrically connecting the contacts of the second microelectronic element to the terminals; and
third leads electrically interconnecting the contacts of the first microelectronic element with the contacts of the second microelectronic element, the first, second, and third leads having portions aligned with the aperture.

### Claim 2 (depends on 1)

The microelectronic assembly as claimed in claim 1, wherein at least one of the first or second leads include wire bonds extending from the contacts of at least one of the first or second microelectronic elements.

### Claim 3 (depends on 1)

The microelectronic assembly as claimed in claim 1, wherein the portions of at least one of the first leads and the second leads aligned with the aperture are portions of monolithic conductive elements having second portions extending along the substrate to the terminals.

### Claim 4 (depends on 1)

The microelectronic assembly as claimed in claim 1, further comprising a spacing element between the front surface of the second microelectronic element and the first surface of the substrate.

### Claim 5 (depends on 1)

The microelectronic assembly as claimed in claim 1, wherein the first microelectronic element includes a chip configured to predominantly perform a logic function.

### Claim 6 (depends on 1)

The microelectronic assembly as claimed in claim 1, wherein the second microelectronic element has a greater number of active devices configured to provide memory storage array function than any other function.

### Claim 7 (depends on 1)

The microelectronic assembly as claimed in claim 1, wherein the first microelectronic element has a greater number of active devices configured to provide memory storage array function than any other function.

### Claim 8 (depends on 1)

A system comprising the microelectronic assembly according to claim 1 and one or more other electronic components electrically connected to the microelectronic assembly.

### Claim 9 (depends on 8)

The system as claimed in claim 8, wherein the terminals are electrically connected to a circuit panel.

### Claim 10 (depends on 9)

The system as claimed in claim 9, further comprising a housing, the microelectronic assembly and the other electronic components being mounted to the housing.

### Claim 11 (depends on 1)

A microelectronic component including first and second microelectronic assemblies, each microelectronic assembly as claimed in claim 1, the first microelectronic assembly electrically connected with and at least partially overlying the second microelectronic assembly.

### Claim 12 (depends on 11)

The microelectronic component as claimed in claim 11, wherein the microelectronic assemblies are electrically connected with one another through joining units arranged adjacent a periphery of the microelectronic component.

### Claim 13 (depends on 12)

The microelectronic component as claimed in claim 12, wherein the joining units are located outside of a depopulated central region of the microelectronic component.

### Claim 14 (depends on 11)

The microelectronic component as claimed in claim 11, wherein some of the microelectronic elements include a volatile random access memory (RAM), and some of the microelectronic elements include nonvolatile flash memory.

### Claim 15 (depends on 11)

The microelectronic component as claimed in claim 11, wherein at least one of the first microelectronic elements is configured predominantly to perform a logic function, and at least one of the second microelectronic elements has a greater number of active devices configured to provide memory storage array function than any other function.

### Claim 16

A microelectronic assembly, comprising:
a substrate having oppositely-facing first and second surfaces and an aperture extending between the first and second surfaces, the substrate having terminals;
a first microelectronic element having a front surface facing the first surface of the substrate, a rear surface remote therefrom, and an edge extending between the front and rear surfaces, the first microelectronic element having a plurality of contacts exposed at the front surface thereof adjacent the edge of the first microelectronic element;
a second microelectronic element having first and second opposed edges, a front surface extending between the first and second edges, and a plurality of contacts disposed in a central region of the front surface thereof remote from the first and second edges, the front surface of the second microelectronic element facing the first microelectronic element and projecting beyond the edge of the first microelectronic element;
a third microelectronic element disposed between first surface of the substrate and the front surface of the second microelectronic element, the third microelectronic element having first and second opposed edges, a front surface extending between the first and second edges, and a plurality of contacts disposed on the front surface thereof adjacent the first edge thereof, the front surface of the third microelectronic element facing the first surface of the substrate;
first leads electrically connecting the contacts of the first microelectronic element to the terminals;
second leads connecting the contacts of the second microelectronic element to the terminals;
third leads electrically connecting the contacts of the third microelectronic element to the terminals; and
fourth leads electrically interconnecting the contacts of the first and third microelectronic elements, the contacts of the first and third microelectronic elements being located on opposite sides of the aperture, the first, second, third, and fourth leads having portions aligned with the aperture.

### Claim 17 (depends on 16)

The microelectronic assembly as claimed in claim 16, further comprising fifth leads electrically interconnecting the contacts of the first and second microelectronic elements.

### Claim 18 (depends on 17)

The microelectronic assembly as claimed in claim 17, further comprising sixth leads electrically interconnecting the contacts of the second and third microelectronic elements.

### Claim 19 (depends on 16)

The microelectronic assembly as claimed in claim 16, wherein the first microelectronic element includes a chip configured to predominantly perform a logic function.

### Claim 20 (depends on 16)

The microelectronic assembly as claimed in claim 16, wherein the second microelectronic element has a greater number of active devices configured to provide memory storage array function than any other function.

### Claim 21 (depends on 16)

The microelectronic assembly as claimed in claim 16, wherein the first microelectronic element has a greater number of active devices configured to provide memory storage array function than any other function.