# US 2018/0025965 A1 · WFCQFN (Very-Very Thin Flip Chip Quad Flat No Lead) with Embedded Component on Leadframe and Method Therefor

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- Number: US 2018/0025965 A1
- Document ID: US20180025965A1
- Status: Published application
- Kind: A1
- Application number: 15/213,559
- Filed: 2016-07-19
- Published: 2018-01-25
- Earliest claimed: 2016-07-19
- Assignees: Dialog Semiconductor (UK) Limited
- Applicants: Dialog Semiconductor (UK) Limited
- Inventors: Baltazar Canete, JR.; Melvin Martin; Ian Kent; Jesus Mennen Belonio, JR.; Rajesh Subraya Aiyandra
- Web page: https://patentgrep.com/patent/US20180025965A1

## CPC

- H10W 90/811: {Multiple chips on leadframes}
- H10W 70/041: {Connecting or disconnecting interconnections to or from leadframes, e.g. connecting bond wires or bumps}
- H10W 70/042: {Etching}
- H10W 70/411: {Chip-supporting parts, e.g. die pads}
- H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)}
- H10W 70/465: {Bumps or wires}
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/016: {using moulds}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 70/048: {Mechanical treatments, e.g. punching, cutting, deforming or cold welding}
- H10W 70/682: {comprising holes having chips therein}
- H10W 72/072: {of bump connectors}
- H10W 72/07255: {changes in materials}
- H10W 72/073: {of die-attach connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/257: {Multiple bump connectors having different materials}
- H10W 72/354: {comprising polymers}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/722: {between stacked chips}
- H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/728: {between a chip and a stacked discrete passive device, e.g. resistors, capacitors or inductors}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A quad flat no lead package is provided comprising at least one first integrated circuit die embedded in a recess in a die paddle of a metal leadframe and a second integrated circuit chip die attached to the at least one first integrated circuit die wherein the first and second integrated circuit dies are electrically connected to each other and wherein the second integrated circuit die is connected to leads of the leadframe through copper pillars.

## Claims

### Claim 1

A quad flat no lead package comprising:
at least one first integrated circuit die embedded in a recess in a die paddle portion of a metal leadframe; and
a second integrated circuit die attached to said at least one first integrated circuit die wherein said first and second integrated circuit dies are electrically connected to each other and wherein said second integrated circuit die is connected to leads of said leadframe through copper pillars.

### Claim 2 (depends on 1)

The package according to claim 1 wherein said at least one first integrated circuit die is an integrated passive device and wherein said second integrated circuit die is a mother die.

### Claim 3 (depends on 1)

The package according to claim 1 wherein said first and second integrated circuit dies are electrically connected to each other through solder bumps.

### Claim 4 (depends on 1)

The package according to claim 1 wherein said package contains no wire bonds.

### Claim 5 (depends on 1)

The package according to claim 1 wherein a top surface of said second integrated circuit is exposed to minimize the package profile and to dissipate heat.

### Claim 6

A method of fabricating a quad flat no lead package comprising:
providing a leadframe having at least one recess formed in a top surface of a die paddle portion of said leadframe;
embedding at least one first integrated circuit die in said at least one recess;
forming solder bumps on said at least one first integrated circuit die;
forming copper pillars on said leadframe and on leads of said leadframe;
dispensing an underfill material surrounding said solder bumps and said copper pillars on said die paddle portion of said leadframe; and
thereafter flip chip attaching a second integrated circuit die to said at least one first integrated circuit die, wherein said first and second integrated circuit dies are electrically connected through said solder bumps and wherein said second integrated circuit die is electrically connected to said die paddle portion of said leadframe and to said leads through said copper pillars and wherein a thickness of said at least one first integrated circuit die does not contribute to a thickness of completed said quad flat no lead package.

### Claim 7 (depends on 6)

The method according to claim 6 further comprising encapsulating said package with a molding compound wherein a top surface of said second integrated circuit die is exposed to complete said quad flat no lead package.

### Claim 8 (depends on 6)

The method according to claim 6 wherein said at least one first integrated circuit die is an integrated passive device and wherein said second integrated circuit die is a mother die.

### Claim 9 (depends on 6)

The method according to claim 6 wherein said package contains no wire bonds.

### Claim 10 (depends on 6)

The method according to claim 6 wherein said at least one recess in said die paddle portion of said leadframe is formed by chemical etching or by a combination of wet and dry etching.

### Claim 11 (depends on 6)

The method according to claim 6 wherein said at least one recess in said die paddle portion of said leadframe is formed by stamping, laser drilling, or dry etching.

### Claim 12 (depends on 6)

The method according to claim 6 wherein there are two or more first integrated circuit dies embedded, each first integrated circuit die embedded in its own recess in said die paddle portion of said leadframe.

### Claim 13

A quad flat no lead package comprising:
at least one first integrated circuit die embedded in a recess in a top surface of a die paddle portion of a metal leadframe; and
a second integrated circuit die attached to said at least one first integrated circuit die wherein said first and second integrated circuit dies are electrically connected to each other and wherein said second integrated circuit die is connected to leads of said leadframe through copper pillars and wherein a thickness of said at least one first integrated circuit die does not contribute to a thickness of completed said quad flat no lead package.

### Claim 14 (depends on 13)

The package according to claim 13 wherein said at least one first integrated circuit die is an integrated passive device and wherein said second integrated circuit die is a mother die.

### Claim 15 (depends on 13)

The package according to claim 13 wherein said first and second integrated circuit dies are electrically connected to each other through solder bumps.

### Claim 16 (depends on 13)

The package according to claim 13 wherein said package contains no wire bonds.

### Claim 17 (depends on 13)

The package according to claim 13 wherein a top surface of said second integrated circuit is exposed to minimize the package profile and to dissipate heat.