# US 2018/0025955 A1 · Semiconductor device and method

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- Number: US 2018/0025955 A1
- Document ID: US20180025955A1
- Status: Published application
- Kind: A1
- Application number: 15/705,567
- Filed: 2017-09-15
- Published: 2018-01-25
- Earliest claimed: 2016-01-14
- Assignees: Chip Solutions, LLC
- Applicants: Chip Solutions, LLC
- Inventors: Sukianto Rusli
- Web page: https://patentgrep.com/patent/US20180025955A1

## CPC

- H10W 70/68: Shapes or dispositions thereof
- H10P 72/06: {Apparatus for monitoring, sorting, marking, testing or measuring}
- H10P 72/10: using carriers specially adapted therefor, e.g. front opening unified pods [FOUP]
- H10P 72/74: {using temporarily an auxiliary support}
- H10P 72/7448: {the bond interface between the auxiliary support and the wafer comprising two or more, e.g. multilayer adhesive or adhesive and release layer}
- H10P 74/23: {characterised by multiple measurements, corrections, marking or sorting processes}
- H10P 74/27: {Structural arrangements therefor}
- H10W 20/42: Vias, e.g. via plugs
- H10W 70/095: {of vias therein}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 74/016: {using moulds}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 90/00: Package configurations
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7412: {the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics}
- H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/635: {Through-vias}
- H10W 70/69: Insulating materials thereof
- H10W 72/072: {of bump connectors}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 80/721: {having structure or size changed during the connecting}
- H10W 80/754: {having material changed during the connecting}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Disclosed herein is a method for forming a semiconductor package. The method includes providing a first releasable chip carrier attached to a conductive layer. A circuit layer is formed on a surface of the conductive layer and a dielectric layer is applied over a surface of the circuit layer. A second releasable chip carrier is attached to a surface of the dielectric layer and the first releasable chip carrier is released from the conductive layer via facilitation of a first activating source. The circuitry of the circuit layer is operationally tested.

## Claims

### Claim 1

A method for forming a semiconductor package comprising:
providing a first releasable chip carrier attached to a conductive layer;
forming a circuit layer on a surface of the conductive layer;
applying a dielectric layer over a surface of the circuit layer;
attaching a second releasable chip carrier to a surface of the dielectric layer;
releasing, via facilitation of a first activating source, the first releasable chip carrier from the conductive layer; and
operationally testing circuitry of the circuit layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein results of said operationally testing indicate that the circuitry is operationally functional, and wherein said method further comprises:
attaching a semiconductor die to portions of the circuit layer;
forming an encapsulating layer surrounding the semiconductor die;
attaching a third releasable chip carrier to a surface of the encapsulating layer; and
releasing, via facilitation of a second activating source, the second releasable chip carrier from the surface of the dielectric layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein the first releasable chip carrier, the second releasable chip carrier, and the third releasable chip carrier each comprise a size format selected from the group consisting of a panel size format and a strip size format.

### Claim 4 (depends on 2)

The method of claim 2, further comprising:
removing portions of said dielectric layer thereby forming openings within the dielectric layer; and
forming ball grid array structures within the openings, wherein the ball grid array structures are electrically connected to the semiconductor die, and wherein the conductive layer, the circuit layer, the dielectric layer, the semiconductor die, the encapsulating layer, and the ball grid array structures form the semiconductor package.

### Claim 5 (depends on 2)

The method of claim 2, wherein the second activating source comprises a same activating source as the first activating source.

### Claim 6 (depends on 2)

The method of claim 2, wherein the second activating source differs from the first activating source.

### Claim 7 (depends on 1)

The method of claim 1, wherein the first releasable chip carrier and the second releasable chip carrier each comprise a panel size format.

### Claim 8 (depends on 1)

The method of claim 1, wherein the first releasable chip carrier comprises a panel size format, and wherein the second releasable chip carrier comprises a strip size format.

### Claim 9 (depends on 1)

The method of claim 1, wherein the first activating source does not make physical contact with the first releasable chip carrier.

### Claim 10 (depends on 1)

The method of claim 1, wherein the applying a dielectric layer over a surface of the circuit layer comprises sequentially applying multiple dielectric layers over the surface of the circuit layer.

### Claim 11 (depends on 1)

The method of claim 1, wherein the first activating source is a heat source, and wherein the method includes raising the temperature of an adhesive located between the first releasable chip carrier and the conductive layer to a temperature between 150° C. and 300° C.

### Claim 12 (depends on 1)

The method of claim 1, wherein the conductive layer includes a thin foil layer and a carrier foil layer, and wherein the releasing the first releasable chip carrier from the conductive layer releases the first releasable chip carrier from the carrier foil layer.

### Claim 13 (depends on 1)

The method of claim 1, further comprising:
forming an adhesive layer between the first releasable chip carrier and the conductive layer; and
activating the adhesive layer with the first activating source to facilitate the releasing.

### Claim 14 (depends on 13)

The method of claim 13, wherein the adhesive layer is a double sided tape, and wherein the method further comprises an application process selected form the group consisting of applying a thermal release adhesive on one or both sides of the double sided tape and applying a UV release adhesive on one or both sides of the double sided tape.

### Claim 15

A method for forming semiconductor packages comprising:
providing a first releasable chip carrier attached to a conductive layer;
forming a circuit layer on a surface of the conductive layer;
applying a dielectric layer over a surface of the circuit layer;
attaching a second releasable chip carrier to a surface of the dielectric layer;
releasing, via facilitation of a first activating source, the first releasable chip carrier from the conductive layer; and
operationally testing first circuitry and second circuitry of the circuit layer.

### Claim 16 (depends on 15)

The method of claim 15, wherein results of said operationally testing indicate that the first circuitry and the second circuitry are each operationally functional, and wherein said method further comprises:
attaching a first semiconductor die to portions of the first circuitry of the circuit layer;
attaching a second semiconductor die to portions of the second circuitry of the circuit layer;
forming an encapsulating layer surrounding the first semiconductor die and the second semiconductor die;
attaching a third releasable chip carrier to a surface of the encapsulating layer;
releasing, via facilitation of a second activating source, the second releasable chip carrier from the surface of the dielectric layer;
removing portions of said dielectric layer thereby forming openings within the dielectric layer;
forming a first group of ball grid array structures and a second group of ball array structures within the openings, wherein the first group of ball grid array structures are electrically connected to the first semiconductor die, wherein the second group of ball grid array structures are electrically connected to the second semiconductor die; and
applying a laser cut between the first semiconductor die and the second semiconductor die and through the conductive layer, the circuit layer, the dielectric layer, and the encapsulating layer thereby forming a first semiconductor structure and a second semiconductor structure as independent singulated semiconductor structures.

### Claim 17

A releasable carrier structure comprising:
a first releasable chip carrier;
a carrier conductive layer;
a first releasable tape layer placed between the first releasable chip carrier and the carrier conductive layer, wherein the first releasable tape layer attaches the first releasable chip carrier to the carrier conductive layer, and wherein the first releasable tape layer is configured to release the first releasable chip carrier from the carrier conductive layer after being exposed to an activating source;
a dielectric layer formed over a surface of a circuit layer formed over the carrier conductive layer;
a second releasable chip carrier; and
a second releasable tape layer placed between the second releasable chip carrier and the dielectric layer, wherein the second releasable tape layer attaches the second releasable chip carrier to the dielectric layer, and wherein the second releasable tape layer is configured to release the second releasable chip carrier from the dielectric layer after being exposed to the activating source.

### Claim 18 (depends on 17)

The releasable carrier structure of claim 17, wherein the first releasable chip carrier and the second releasable chip carrier each comprise a size format selected from the group consisting of a panel size format and a strip size format.

### Claim 19 (depends on 17)

The releasable carrier structure of claim 17, wherein the first releasable chip carrier and the second releasable chip carrier each comprise a panel size format.

### Claim 20 (depends on 17)

The releasable carrier structure of claim 17, wherein the first releasable chip carrier comprises a panel size format, and wherein the second releasable chip carrier comprises a strip size format.