# US 2018/0025954 A1 · Top contact resistance measurement in vertical fets

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- Number: US 2018/0025954 A1
- Document ID: US20180025954A1
- Status: Published application
- Kind: A1
- Application number: 15/622,614
- Filed: 2017-06-14
- Published: 2018-01-25
- Earliest claimed: 2016-07-25
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Kangguo Cheng; Zuoguang Liu; Xin Miao; Wenyu Xu; Chen Zhang
- Web page: https://patentgrep.com/patent/US20180025954A1

## CPC

- H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads}
- G01R 27/205: {Measuring contact resistance of connections, e.g. of earth connections}
- G01R 31/2621: {for testing field effect transistors, i.e. FET's}
- G01R 31/2813: {Checking the presence, location, orientation or value, e.g. resistance, of components or conductors (orientation of the DUT with respect to the test fixture G01R1/06705)}
- H10D 8/01: Manufacture or treatment
- H10D 8/043: {of planar diodes}
- H10D 8/045: {of PN junction diodes}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/0291: {of vertical DMOS [VDMOS] FETs}
- H10D 30/477: {Vertical HEMTs or vertical HHMTs}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6728: {Vertical TFTs}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/6758: {characterised by the insulating substrates}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/0195: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 86/011: {comprising FinFETs}
- H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics}
- H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers}
- H10W 20/031: {of conductive parts of the interconnections}
- G01R 31/2856: {Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]}
- H10D 84/016: {the components including vertical IGFETs}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A test device includes a diode junction layer having a first dopant conductivity region and a second dopant conductivity region formed within the diode junction layer on opposite sides of a diode junction. A first portion of vertical transistors is formed over the first dopant conductivity region as a device under test, and a second portion of vertical transistors is formed over the second dopant conductivity region. A common source/drain region is formed over the first and second portions of vertical transistors. Current through the first portion of vertical transistors permits measurement of a resistance at a probe contact connected to the common source/drain region.

## Claims

### Claim 1

A test device, comprising:
a diode junction layer having a first dopant conductivity region and a second dopant conductivity region formed within the diode junction layer on opposite sides of a diode junction; and
a first portion of vertical transistors formed over the first dopant conductivity region as a device under test and a second portion of vertical transistors formed over the second dopant conductivity region.

### Claim 2 (depends on 1)

The device as recited in claim 1, wherein the vertical transistors are formed vertically along semiconductor fins such that a device channel for the vertical transistors is disposed in a normal direction relative to the diode junction layer.

### Claim 3 (depends on 2)

The device as recited in claim 2, wherein the first portion of vertical transistors includes whole fins.

### Claim 4 (depends on 2)

The device as recited in claim 2, wherein the first portion of vertical transistors includes part of fins that extends into a device under test region and part that extends into a test setup region outside the device under test region.

### Claim 5 (depends on 1)

The device as recited in claim 1, further comprising a common gate structure that serves both the first and second portions of vertical transistors.

### Claim 6 (depends on 1)

The device as recited in claim 1, a common source/drain region formed over the first and second portions of vertical transistors, wherein the diode junction actively prevents lateral current flow in the common source/drain region to measure sense potential.

### Claim 7 (depends on 6)

The device as recited in claim 6, wherein a source voltage of the device under test is maintained at substantially zero to measure the sense potential.

### Claim 8 (depends on 6)

The device as recited in claim 6, wherein current through the first portion of vertical transistors permits measurement of a resistance at a probe contact connected to the common source/drain region.

### Claim 9

A test device, comprising:
a diode junction layer having a first dopant conductivity region and a second dopant conductivity region formed within the diode junction layer on opposite sides of a diode junction, the first dopant conductivity region including a vertical transistor drain for a device under test; and
a first portion of vertical transistors formed over the first dopant conductivity region as the device under test and a second portion of vertical transistors formed over the second dopant conductivity region, wherein the vertical transistors are formed vertically along semiconductor fins such that a device channel for the vertical transistors is disposed in a normal direction relative to the diode junction layer.

### Claim 10 (depends on 9)

The device as recited in claim 9, wherein the first portion of vertical transistors includes whole fins.

### Claim 11 (depends on 9)

The device as recited in claim 9, wherein the first portion of vertical transistors includes part of fins that extends into a device under test region and part that extends into a test setup region outside the device under test region.

### Claim 12 (depends on 9)

The device as recited in claim 9, further comprising a common gate structure that serves both the first and second portions of vertical transistors.

### Claim 13 (depends on 9)

The device as recited in claim 9, a common source/drain region formed over the first and second portions of vertical transistors, the common source/drain region including a vertical transistor source for the device under test, wherein current through the first portion of vertical transistors permits measurement of a resistance at a probe contact connected to the common source/drain region and wherein the diode junction actively prevents lateral current flow in the common source/drain region to measure sense potential.

### Claim 14 (depends on 13)

The device as recited in claim 13, wherein a source voltage of the device under test is maintained at substantially zero to measure the sense potential.

### Claim 15 (depends on 13)

The device as recited in claim 13, further comprising a drain contact formed on the drain, a source contact formed on a device under test side of the common source/drain region and the probe contact formed on a test setup side of the common source/drain region.