# US 2018/0025952 A1 · Reverse Decoration for Defect Detection Amplification

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2018/0025952 A1
- Document ID: US20180025952A1
- Status: Published application
- Kind: A1
- Application number: 15/390,473
- Filed: 2016-12-24
- Published: 2018-01-25
- Earliest claimed: 2016-07-20
- Assignees: KLA-Tencor Corporation
- Applicants: KLA-Tencor Corporation
- Inventors: Philip Measor; Robert Danen; Paul MacDonald
- Web page: https://patentgrep.com/patent/US20180025952A1

## CPC

- H10P 74/232: {comprising connection or disconnection of parts of a device in response to a measurement}
- G01R 31/2898: {Sample preparation, e.g. removing encapsulation, etching (sample preparation in general G01N1/00)}
- H10P 50/644: {Anisotropic liquid etching (H10P50/61 takes precedence)}
- H10P 52/402: {of semiconductor materials}
- H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects}
- H10P 74/235: {comprising optical enhancement of defects or not-directly-visible states}
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Reverse decoration can be used to detect defects in a device. The wafer can include NAND stacks or other devices. The defect can be a channel bridge, a void, or other types of defects. Reverse decoration can preserve a defect and/or can improve defect detection. A portion of a layer may be removed from a device. A layer also may be added to the device, such as on the defect, and some of the layer may be removed.

## Claims

### Claim 1

A method comprising:
applying a layer of a material on a surface of a wafer such that a defect on the wafer is covered with the layer, wherein the material is configured to amplify detection of the defect; and
removing a first portion of the layer, wherein a second portion of the layer is configured to remain disposed on the defect after the removing.

### Claim 2 (depends on 1)

The method of claim 1, wherein the defect is a void, a bridge, or a separation.

### Claim 3 (depends on 1)

The method of claim 1, wherein the material is silicon nitride, polysilicon, titanium dioxide, amorphous carbon, hafnium oxide, magnesium oxide, aluminum oxide, silicon carbide, tantalum pentoxide, or a combination thereof.

### Claim 4 (depends on 1)

The method of claim 1, wherein the removing includes at least one of etching or chemical mechanical planarization.

### Claim 5 (depends on 1)

The method of claim 1, wherein the applying includes depositing.

### Claim 6 (depends on 1)

The method of claim 1, wherein the material is further configured to preserve the defect during the removing.

### Claim 7 (depends on 1)

The method of claim 1, wherein the second portion of the layer remaining disposed on the defect has a thickness from 1 nm to 500 nm.

### Claim 8 (depends on 1)

The method of claim 1, wherein the surface includes at least one NAND stack.

### Claim 9 (depends on 1)

The method of claim 1, wherein the surface includes at least one structure containing copper or tungsten, and wherein the defect is disposed in the structure.

### Claim 10 (depends on 1)

The method of claim 1, further comprising detecting the defect after the removing.

### Claim 11

A method comprising:
applying a layer of a material on a surface of a wafer such that a defect on the wafer is covered with the layer, wherein the surface of the wafer includes a plurality of NAND stacks, and wherein the material is configured to amplify detection of the defect; and
removing a first portion of the layer, wherein a second portion of the layer is configured to remain disposed on the defect after the removing.

### Claim 12 (depends on 11)

The method of claim 11, wherein the defect is a void in a wall of one of the NAND stacks, wherein the applying includes isotropic deposition on the walls of the NAND stacks, and wherein the removing includes isotropic etching of the walls of the NAND stacks.

### Claim 13 (depends on 11)

The method of claim 11, wherein the defect is a bridge structure between two of the NAND stacks, wherein the applying includes anisotropic deposition on the walls of the NAND stacks, and wherein the removing includes isotropic etching of the walls of the NAND stacks.

### Claim 14 (depends on 11)

The method of claim 11, wherein the material is silicon nitride, polysilicon, titanium dioxide, amorphous carbon, hafnium oxide, magnesium oxide, aluminum oxide, silicon carbide, tantalum pentoxide, or a combination thereof.

### Claim 15 (depends on 11)

The method of claim 11, wherein the second portion of the layer remaining disposed on the defect has a thickness from 1 nm to 500 nm.

### Claim 16

A method comprising:
providing a wafer including a NAND stack with a defect, wherein the defect is a void in a wall of the NAND stack;
removing some tungsten from the NAND stack, wherein removing the tungsten is configured to expose a surface of a pillar in the NAND stack;
removing silicon from the NAND stack, wherein removing the silicon forms a void in the pillar; and
removing a remainder of the tungsten from the NAND stack.

### Claim 17 (depends on 16)

The method of claim 16, wherein removing the tungsten includes an isotropic etch, and wherein some of the tungsten is configured to remain on the NAND stack after removing the tungsten.

### Claim 18 (depends on 16)

The method of claim 16, wherein removing the silicon includes an etch.