# US 2018/0025946 A1 · FINFET Channel on Oxide Structures and Related Methods

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- Number: US 2018/0025946 A1
- Document ID: US20180025946A1
- Status: Published application
- Kind: A1
- Application number: 15/714,557
- Filed: 2017-09-25
- Published: 2018-01-25
- Earliest claimed: 2015-06-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Kuo-Cheng Ching; Ching-Wei TSAI; Ying-Keung LEUNG
- Web page: https://patentgrep.com/patent/US20180025946A1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/834: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for fabricating a semiconductor device having a substantially undoped channel region includes forming a plurality of fins extending from a substrate. In various embodiments, each of the plurality of fins includes a portion of a substrate, a portion of a first epitaxial layer on the portion of the substrate, and a portion of a second epitaxial layer on the portion of the first epitaxial layer. The portion of the first epitaxial layer of each of the plurality of fins is oxidized, and a liner layer is formed over each of the plurality of fins. Recessed isolation regions are then formed adjacent to the liner layer. The liner layer may then be etched to expose a residual material portion (e.g., Ge residue) adjacent to a bottom surface of the portion of the second epitaxial layer of each of the plurality of fins, and the residual material portion is removed.

## Claims

### Claim 1

A semiconductor device, comprising:
a plurality of fin elements extending from a substrate, wherein each of the plurality of fin elements includes a first semiconductor layer, a dielectric layer over the first semiconductor layer, and a second semiconductor layer over the dielectric layer, wherein the second semiconductor layer includes a bottom surface that defines a first horizontal plane;
a recessed isolation region adjacent to the plurality of fin elements, wherein the recessed isolation region includes a top surface adjacent to the second semiconductor layer, wherein the top surface defines a second horizontal plane, and wherein the second horizontal plane is disposed above the first horizontal plane; and
a gate stack formed over the second semiconductor layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further including a liner layer adjacent to and in contact with the first semiconductor layer.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the first semiconductor layer includes Si, the dielectric layer includes oxidized SiGe, the second semiconductor layer includes Si, and the liner layer includes silicon nitride.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, further including:
the recessed isolation region, wherein the recessed isolation region includes a first dielectric material, and wherein the first dielectric material includes a void interposing the bottom surface of the second semiconductor layer and the recessed isolation region; and
a second dielectric material that fills the void.

### Claim 5

A semiconductor device, comprising:
a fin extending from a substrate, the fin including a gate stack region and source/drain regions disposed adjacent to and on either side of the gate stack region, wherein within the gate stack region the fin includes a first semiconductor layer, a dielectric layer over the first semiconductor layer, and a second semiconductor layer over the dielectric layer, the second semiconductor layer having a bottom surface that defines a first horizontal plane, and wherein within the source/drain regions the fin includes the first semiconductor layer and a source/drain layer over the first semiconductor layer; and
an isolation region adjacent to the fin, wherein the isolation region includes a top surface that defines a second horizontal plane, and wherein the second horizontal plane is disposed substantially co-planar with or above the first horizontal plane.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, further including a gate stack formed over the second semiconductor layer within the gate stack region.

### Claim 7 (depends on 5)

The semiconductor device of claim 5, wherein the second horizontal plane is disposed substantially co-planar with the first horizontal plane.

### Claim 8 (depends on 5)

The semiconductor device of claim 5, wherein the second horizontal plane is disposed above the first horizontal plane.

### Claim 9 (depends on 5)

The semiconductor device of claim 5, further including a liner layer adjacent to and in contact with the first semiconductor layer in each of the gate stack region and the source/drain regions.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the first semiconductor layer includes Si, the dielectric layer includes oxidized SiGe, the second semiconductor layer includes Si, and the liner layer includes silicon nitride.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, further including:
the isolation region, wherein the isolation region includes a first dielectric material, and wherein the first dielectric material includes a void interposing the bottom surface of the second semiconductor layer and the isolation region; and
a second dielectric material that fills the void.

### Claim 12 (depends on 5)

The semiconductor device of claim 5, wherein the source/drain layer includes Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, SiC, or SiCP.

### Claim 13 (depends on 5)

The semiconductor device of claim 5, wherein the first semiconductor layer includes an anti-punch through (APT) dopant and residual Ge disposed on opposing sidewalls of a top portion of the first semiconductor layer.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein a concentration of the APT dopant is between about 1×1018 cm−3 and 1×1019 cm−3.

### Claim 15

A semiconductor device, comprising:
a plurality of fin elements, wherein each of the plurality of fin elements includes a first layer, an oxidized layer over the first layer, and a second layer over the oxidized layer, wherein the second layer includes a top surface and a bottom surface, wherein the second layer has a height defined as a first distance between the top and bottom surfaces, and wherein the bottom surface defines a first horizontal plane;
a dielectric region adjacent to the plurality of fins, wherein the dielectric region is recessed by a second distance measured from the top surface of the second layer, wherein the dielectric region includes a top dielectric surface adjacent to the second layer, wherein the top dielectric surface defines a second horizontal plane, and wherein the second horizontal plane is disposed substantially co-planar with or above the first horizontal plane; and
a gate stack formed over the second semiconductor layer.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the second horizontal plane is disposed substantially co-planar with the first horizontal plane.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein the second horizontal plane is disposed above the first horizontal plane.

### Claim 18 (depends on 16)

The semiconductor device of claim 16, wherein the second distance is substantially equal to the first distance.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, wherein the second distance is less than the first distance.

### Claim 20 (depends on 15)

The semiconductor device of claim 15, wherein the height of the second layer is between about 30-60 nm.