# US 2018/0025942 A1 · Self-aligned contact cap

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- Number: US 2018/0025942 A1
- Document ID: US20180025942A1
- Status: Published application
- Kind: A1
- Application number: 15/216,154
- Filed: 2016-07-21
- Published: 2018-01-25
- Earliest claimed: 2016-07-21
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Kangguo Cheng; Peng Xu
- Web page: https://patentgrep.com/patent/US20180025942A1

## CPC

- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/679: {comprising air gaps}
- H10W 20/0698: {Local interconnections}
- H10W 20/074: {of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers}
- H10W 20/082: {the openings being tapered via holes}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for forming a semiconductor device includes recessing a gate conductor in a gate structure to form a first divot, forming a gate cap in the first divot and recessing a dielectric fill that encapsulates the gate structures to a position below a top of the gate cap. An extension layer is deposited over the dielectric fill and the top of the gate cap and is planarized to the top of the gate cap. The extension layer is expanded to form a profile growth layer that is thicker than the extension layer and creates a second divot over the gate cap. A top cap is formed in the second divot to provide a cap with a thickness of the gate cap and the top cap.

## Claims

### Claim 1

A method for forming a semiconductor device, comprising:
recessing a gate conductor in a gate structure to form a first divot;
forming a gate cap in the first divot;
recessing a dielectric fill that encapsulates the gate structures to a position below a top of the gate cap;
depositing an extension layer over the dielectric fill and the top of the gate cap;
planarizing the extension layer to the top of the gate cap;
expanding the extension layer to form a profile growth layer that is thicker than the extension layer and creates a second divot over the gate cap; and
forming a top cap in the second divot to provide a cap with a thickness of the gate cap and the top cap.

### Claim 2 (depends on 1)

The method as recited in claim 1, wherein recessing the gate conductor includes recessing the gate conductor without interfacing with a seam formed within the gate conductor.

### Claim 3 (depends on 1)

The method as recited in claim 1, wherein depositing the extension layer includes depositing a polysilicon layer.

### Claim 4 (depends on 3)

The method as recited in claim 3, wherein expanding the extension layer includes oxidizing the polysilicon layer to form the profile growth layer having second divots formed therein.

### Claim 5 (depends on 4)

The method as recited in claim 4, further comprising isotropically etching the profile growth layer to shape the second divots.

### Claim 6 (depends on 1)

The method as recited in claim 1, further comprising:
forming an interlevel dielectric (ILD) layer over the gate structure; and
etching self-aligned contact openings through the (ILD) with the top cap exposed to the etching.

### Claim 7 (depends on 1)

The method as recited in claim 1, wherein expanding the extension layer includes expanding the extension layer by about 100% in thickness.

### Claim 8

A method for forming a semiconductor device, comprising:
forming a dummy gate;
forming spacers on sidewalls of the dummy gate to form gate structures;
filling between the gate structures with a dielectric fill;
replacing the dummy gate with a replacement gate having a gate conductor formed by deposition;
recessing the gate conductor in the gate structure to form a first divot that is shallow enough not to interfere with a potential seam formed during gate conductor formation;
forming a gate cap in the first divot;
recessing a dielectric fill that encapsulates the gate structures to a position below a top of the gate cap;
depositing an extension layer over the dielectric fill and the top of the gate cap;
planarizing the extension layer to the top of the gate cap;
expanding the extension layer to form a profile growth layer that is thicker than the extension layer and creates a second divot over the gate cap; and
forming a top cap in the second divot to provide a cap with a thickness of the gate cap and the top cap.

### Claim 9 (depends on 8)

The method as recited in claim 8, wherein depositing the extension layer includes depositing a polysilicon layer.

### Claim 10 (depends on 9)

The method as recited in claim 9, wherein expanding the extension layer includes oxidizing the polysilicon layer to form the profile growth layer having second divots formed therein.

### Claim 11 (depends on 10)

The method as recited in claim 10, further comprising isotropically etching the profile growth layer to shape the second divots.

### Claim 12 (depends on 9)

The method as recited in claim 9, further comprising:
forming an interlevel dielectric (ILD) layer over the gate structure; and
etching self-aligned contact openings through the (ILD) with the top cap exposed to the etching.

### Claim 13 (depends on 9)

The method as recited in claim 9, wherein expanding the extension layer includes expanding the extension layer by about 100% in thickness.

### Claim at position 14

-20. (canceled)