# US 2018/0025934 A1 · Semiconductor integrated circuit device having electrostatic discharge protection circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0025934 A1 - Document ID: US20180025934A1 - Status: Published application - Kind: A1 - Application number: 15/613,780 - Filed: 2017-06-05 - Published: 2018-01-25 - Earliest claimed: 2016-07-19 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Yun Seok HONG - Web page: https://patentgrep.com/patent/US20180025934A1 ## CPC - H10W 29/00: Generic parts of integrated devices, not otherwise provided for - H05F 3/02: by means of earthing connections - H10B 63/24: {of the Ovonic threshold switching type} - H10D 89/911: {using passive elements as protective elements} - H10N 70/882: {Compounds of sulfur, selenium or tellurium, e.g. chalcogenides} - H10W 15/00: Highly-doped buried regions of integrated devices - H10W 15/01: {Manufacture or treatment} - H10W 29/01: {Manufacture or treatment} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H05F: STATIC ELECTRICITY; NATURALLY-OCCURRING ELECTRICITY - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR ## Abstract A semiconductor integrated circuit device may include a first electrostatic discharge (ESD) protecting circuit and a second ESD protecting circuit. The first ESD protecting circuit may include at least one resistance changeable device connected between a power voltage line and a data pad to discharge an electrostatic. The second ESD protecting circuit may include at least one resistance changeable device connected between the first ESD protecting circuit and a ground voltage line. ## Claims ### Claim 1 A semiconductor integrated circuit device comprising: a first electrostatic discharge (ESD) protecting circuit including at least one resistance changeable device connected between a power voltage line and a data pad to discharge electrostatic charges; and a second ESD protecting circuit including at least one resistance changeable device connected between the first ESD protecting circuit and a ground voltage line. ### Claim 2 (depends on 1) The semiconductor integrated circuit device of claim 1, wherein the resistance changeable device is an ovonic threshold switch (OTS) device. ### Claim 3 (depends on 2) The semiconductor integrated circuit device of claim 2, wherein the OTS device comprises: a first electrode; a chalcogenide layer formed on the first electrode; and a second electrode formed on the chalcogenide layer. ### Claim 4 (depends on 2) The semiconductor integrated circuit device of claim 2, wherein the first ESD protecting circuit comprises a plurality of the OTS devices connected to each other in series. ### Claim 5 (depends on 4) The semiconductor integrated circuit device of claim 4, wherein the OTS devices are stacked on a semiconductor substrate. ### Claim 6 (depends on 4) The semiconductor integrated circuit device of claim 4, wherein the first ESD protecting circuit further comprises a resistor connected between the OTS devices and the data pad. ### Claim 7 (depends on 4) The semiconductor integrated circuit device of claim 4, wherein the first ESD protecting circuit further comprises an NMOS transistor configured to connect the power voltage line to the ground voltage line in response to an output signal from the OTS devices. ### Claim 8 (depends on 2) The semiconductor integrated circuit device of claim 2, wherein the second ESD protecting circuit comprises a plurality of the OTS devices connected to each other in series. ### Claim 9 (depends on 8) The semiconductor integrated circuit device of claim 8, wherein the OTS devices are stacked on a semiconductor substrate. ### Claim 10 (depends on 8) The semiconductor integrated circuit device of claim 8, wherein the first ESD protecting circuit further comprises a resistor connected between the OTS devices and the data pad. ### Claim 11 (depends on 8) The semiconductor integrated circuit device of claim 8, wherein the first ESD protecting circuit further comprises an NMOS transistor configured to connect the power voltage line to the ground voltage line in response to an output signal from the OTS devices. ### Claim 12 (depends on 1) The semiconductor integrated circuit device of claim 1, further comprising a clamping circuit connected between the power voltage line and the ground voltage line. ### Claim 13 (depends on 12) The semiconductor integrated circuit device of claim 12, wherein the clamping circuit comprises: a capacitor connected to the power voltage line; a resistor connected between the capacitor and the ground voltage line; and a switching transistor configured to transfer electrostatic charges in the power voltage line to the ground voltage line in response to a voltage at a connection node between the capacitor and the resistor. ### Claim 14 (depends on 2) The semiconductor integrated circuit device of claim 2, further comprising a charge device model (CDM) discharge protecting circuit connected between the data pad and the internal circuit to discharge the electrostatic charges through the power voltage line or the ground voltage line. ### Claim 15 (depends on 14) The semiconductor integrated circuit device of claim 14, wherein the CDM discharge protecting circuit comprises: a resistor connected with the data pad; a first CDM discharge protecting circuit connected between the power voltage line and the resistor; and a second CDM discharge protecting circuit connected between the first CDM discharge protecting circuit and the ground voltage line. ### Claim 16 (depends on 15) The semiconductor integrated circuit device of claim 15, wherein the first CDM discharge protecting circuit comprises at least one OTS device. ### Claim 17 (depends on 15) The semiconductor integrated circuit device of claim 15, wherein the second CDM discharge protecting circuit comprises at least one OTS device. ### Claim 18 A semiconductor integrated circuit device comprising: a power voltage line connected to a power voltage pad; a ground voltage line connected to a ground voltage pad; a first electrostatic discharge (ESD) protecting circuit connected to a data pad and the power voltage line; a second ESD protecting circuit connected to the data pad, the first ESD protecting circuit, and the ground voltage line; and a charge device model (CDM) discharge protecting circuit connected between an internal circuit and a connection node of the first and second ESD protecting circuits, wherein at least one of the first ESD protecting circuit, the second ESD protecting circuit, and the CDM discharge protecting circuit comprises at least one resistance changeable device. ### Claim 19 (depends on 18) The semiconductor integrated circuit device of claim 18, wherein the resistance changeable device is an ovonic threshold switch (OTS) device. ### Claim 20 (depends on 19) The semiconductor integrated circuit device of claim 19, wherein the CDM discharge protecting circuit includes two or more OTS devices serially connected to each other.