# US 2018/0025911 A1 · Monolithic Integration of Semiconductor Materials

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- Number: US 2018/0025911 A1
- Document ID: US20180025911A1
- Status: Published application
- Kind: A1
- Application number: 15/652,786
- Filed: 2017-07-18
- Published: 2018-01-25
- Earliest claimed: 2016-07-20
- Assignees: Imec Vzw
- Applicants: Imec Vzw
- Inventors: Amey Mahadev Walke; Nadine Collaert; Rita Rooyackers
- Web page: https://patentgrep.com/patent/US20180025911A1

## CPC

- H10P 10/128: {by direct semiconductor to semiconductor bonding}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D 30/472: {having lower bandgap active layer formed on top of wider bandgap layer, e.g. inverted HEMT}
- H10D 30/4755: {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 62/40: Crystalline structures
- H10D 62/605: {Planar doped, e.g. atomic-plane doped or delta-doped}
- H10D 62/85: being Group III-V materials, e.g. GaAs
- H10D 86/011: {comprising FinFETs}
- H10P 14/2907: {being Group IIIA-VA materials}
- H10P 90/1914: {using bonding}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10W 20/0698: {Local interconnections}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 90/00: Package configurations
- H10D 62/852: being Group III-V materials comprising three or more elements, e.g. AlGaN or InAsSbP
- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H10W 72/07355: {changes in materials}
- H10W 72/351: {Materials of die-attach connectors}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for forming a semiconductor structure by bonding a donor substrate to a carrier substrate is disclosed herein. The donor substrate may include a plurality of semiconductor layers epitaxially grown on top of one another in, and optionally above, a trench of the donor substrate. The carrier substrate may include a first semiconductor device thereon. The method may include removing at least part of the donor substrate in such a way as to expose a semiconductor layer grown on the bottom of the trench, removing at least part of the exposed semiconductor layer, thereby modifying the plurality of semiconductor layers, and forming a second semiconductor device from the modified plurality of semiconductor layers.

## Claims

### Claim 1

A method for forming a semiconductor structure, comprising:
providing a donor substrate having a trench therein and having a plurality of semiconductor layers epitaxially grown on top of one another on the donor substrate in such a way that at least a first semiconductor layer of the plurality of semiconductor layers is present in the trench, wherein the trench:
(i) opens toward a top of the donor substrate,
(ii) is defined by a monocrystalline bottom and non-crystalline sidewalls, and
(iii) comprises a width in the range of 10 nm to 10 μm;
providing a carrier substrate comprising:
(i) a semiconductor substrate at a bottom of the carrier substrate,
(ii) a first semiconductor device on the semiconductor substrate, and
(iii) electrical contacts to the first semiconductor device at a top of the carrier substrate;
bonding the donor substrate to the carrier substrate with the top of the donor substrate and the top of the carrier substrate facing each other;
removing at least part of the donor substrate in such a way as to expose the first semiconductor layer, wherein the first semiconductor layer is grown on the monocrystalline bottom of the trench; and
removing at least part of the exposed first semiconductor layer, thereby modifying the plurality of semiconductor layers.

### Claim 2 (depends on 1)

The method of claim 1, further comprising forming a second semiconductor device from the modified plurality of semiconductor layers.

### Claim 3 (depends on 1)

The method of claim 1, wherein the trench comprises a bottom portion having a V-shaped vertical cross-section.

### Claim 4 (depends on 3)

The method of claim 3, wherein the vertical cross-section is taken perpendicularly to a longitudinal direction of the trench.

### Claim 5 (depends on 3)

The method of claim 3, wherein the bottom portion of the trench is defined by two crystalline planes having Miller indices {111}.

### Claim 6 (depends on 1)

The method of claim 1, wherein at least one semiconductor layer of the plurality of semiconductor layers has a top surface comprising less than 108 threading dislocations per cm2.

### Claim 7 (depends on 6)

The method of claim 6, wherein the first semiconductor layer grown on the monocrystalline bottom has a top surface comprising less than 108 threading dislocations per cm2.

### Claim 8 (depends on 1)

The method of claim 1, further comprising, before bonding the donor substrate to the carrier substrate, providing a bonding layer on top of the donor substrate, the carrier substrate, or both.

### Claim 9 (depends on 8)

The method of claim 8, wherein the bonding layer is a dielectric layer.

### Claim 10 (depends on 8)

The method of claim 8, wherein the bonding layer comprises an oxide or a nitride.

### Claim 11 (depends on 8)

The method of claim 8, wherein the plurality of semiconductor layers comprises a layer of channel material, and wherein bonding the donor substrate to the carrier substrate forms a bonded structure in which the bonding layer is directly in contact with the layer of channel material.

### Claim 12 (depends on 1)

The method of claim 1, wherein a delta doping monolayer is present within at least one semiconductor layer of the plurality of semiconductor layers.

### Claim 13 (depends on 12)

The method of claim 12, wherein the delta doping monolayer is located away from a center of the thickness of the layer of channel material.

### Claim 14 (depends on 1)

The method of claim 1, wherein the trench has a depth to width aspect ratio smaller than 2:1.

### Claim 15 (depends on 2)

The method of claim 2 wherein forming the second semiconductor device from the modified plurality of semiconductor layers comprises patterning the modified plurality of semiconductor layers to form the second semiconductor device.

### Claim 16 (depends on 1)

The method of claim 1, wherein the first semiconductor device comprises a complementary metal-oxide-semiconductor device, and wherein the second semiconductor device comprises a radio-frequency device.

### Claim 17 (depends on 1)

The method of claim 1, wherein the second semiconductor device comprises a high-electron-mobility transistor or a metal-oxide-semiconductor field-effect transistor.

### Claim 18 (depends on 1)

The method of claim 1, wherein, during or after bonding the donor substrate to the carrier substrate, the carrier substrate is kept at temperatures not exceeding 500° C.

### Claim 19 (depends on 1)

The method of claim 1, wherein only the first semiconductor layer of the plurality of semiconductor layers is present in the trench, and wherein removing at least part of the exposed first semiconductor layer comprises removing the entire first semiconductor layer.

### Claim 20

A semiconductor structure, comprising:
a semiconductor wafer;
a first semiconductor device on the semiconductor wafer, the first semiconductor device comprising one or more group IV semiconductors;
electrical contacts coupled to the first semiconductor device; and
a second semiconductor device bonded on top of the first semiconductor device, the second semiconductor device comprising one or more III-V materials, wherein the second semiconductor device at least partially overlaps the first semiconductor device.